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Description APPLE INC has the following available in Austin, Texas. Work closely with Architecture to understand performance goals of the design. Correlate RTL performance against model performance. Perform deep performance analysis in the design and report findings. Identify performance bottlenecks in design and coordinate with Architecture team to improve performance. Define performance statistics to help performance debug and standard methodologies to improve performance correlation effort. Have strong interpersonal skills, work independently & lead work you are doing to align with the project goals plus support multi-functional engineering efforts. 40 hours/week.
Minimum Qualifications Bachelor's degree or foreign equivalent in Computer Engineering, Electrical Engineering or related field.
Experience and/or education must include:
Understanding Computer Architecture (to include Cache behavior, and basic CPU operations ) to analyze Performance in complex SoC. Reading and writing Verilog, System Verilog coding to develop or modify UVM testbench Utilizing Python/Perl scripting skills to analyze data and interpret large datasets, including experience in automation, and experience creating custom reporting and internal tools. Lead collaborations between Design, DV and Architecture stakeholders to implement test plans and debug performance shortfalls. Utilizing Excel and CSV file creation and data generation for Data Visualization. Understanding of SoC Fabric/Interconnect design and tradeoffs to optimize for Bandwidth and/or Latency as well as Quality-of-Service metrics. Utilizing engineering and problem solving skills to work with other Engineers to design multiple experiments to isolate issues. Debugging Waveforms using Verdi/Indago to analyze cycle-by-cycle operations of complex state machines.
Preferred Qualifications N/A
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