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Added 19 hours ago
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Principal Design Verification Engineer (Design or DV)
Microsoft
CA · WA · NC · Mountain View, CA · Redmond, WA · Raleigh, NC · Mountain View · Redmond · Raleigh
- $142,800 to $304,200 USD / year
Technically lead A Subsystem as a design or DV engineer.
Added 1 day ago
Head of Memory Architecture (Xora Portfolio Company)
Xora Innovation
Remote, United States
In your role as Head of Memory Architecture, you will lead the architectural design of our disruptive product which is a purpose-built memory for AI inference computing, building on your…
Added 1 day ago
Flight Software Engineer (Rust)
Umbra
Santa Barbara, CA
…tests an array of critical components and subsystems, including power systems, communications, control systems, deployment hardware, avionics, and payloads, as well as the flight software,…
Added 1 day ago
Flight Software Engineer (Rust)
Umbra
Arlington, VA
…tests an array of critical components and subsystems, including power systems, communications, control systems, deployment hardware, avionics, and payloads, as well as the flight software,…
Added 1 day ago
Flight Software Engineer (Rust)
Umbra
Reston, VA
…tests an array of critical components and subsystems, including power systems, communications, control systems, deployment hardware, avionics, and payloads, as well as the flight software,…
Added 4 days ago
ASIC Design Technical Lead (CPU subsystems)
Cisco Systems, Inc.
San Jose, CA
We are seeking a highly experienced designer to lead the architecture and design of complex CPU subsystems for our next-generation high-performance networking switch ASICs. You will use…
Added 5 days ago
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Senior Principal Verification Engineer
Microsoft
NC · TX · Raleigh, NC · Austin, TX · Raleigh · Austin
- $165,600 to $331,200 USD / year
Lead verification of critical SoC functionality including interconnect, coherency, memory, I/O, security, power management, reset, debug, and system-level flows.
Added 8 days ago
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SoC Design Engineer
Solidigm
San Jose, CA
- $167,360 to $267,800 USD / year
…people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, California, Solidigm combines elements of an established, successful technology…
Added 8 days ago
SOC Engineering, Principal Engineer
Synopsys
Austin, TX
Lead subsystem and SoC verification from requirements review and planning through environment development, regression execution, coverage closure, and sign-off.
Added 9 days ago
Solutions Engineering Architect - 19495
Synopsys
Sunnyvale, CA
You have spent a decade or more building, integrating, or supporting complex SoC architectures, and somewhere along the way you realized that the most interesting problems are not just…
Added 9 days ago
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Systems Solutions Architect
Cadence
United States
- $185,500 to $344,500 USD / year
The Cadence SSG Central Applications Engineering team is seeking a Systems Solutions Architect and Technical Lead to define compute-centric solutions for Physical AI. In this role, your…
Added 9 days ago
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Silicon Design Lead
OpenAI
San Francisco, CA
- $287,000 to $485,000 USD / year
- Ideally, have broader SoC-level architecture or integration experience, though deep IP or subsystem-level expertise is sufficient.
Added 11 days ago
SoC Power Architect, Devices and Services, Silicon
Google
Mountain View, CA
Own and drive cross-functional teams to deliver on competitive power key performance indicator (KPIs) for one or more major SoC IPs such as memory subsystem, multimedia subsystem, etc.
Added 11 days ago
SoC Power Lead, Memory Subsystem
Google
Mountain View, CA · San Diego, CA
Experience with memory subsystem architectures, cache hierarchies, system-level power and performance modeling, SoC-wide traffic analysis and optimizations, LPDDR standards, etc.
Added 14 days ago
Principal Analog Design Engineer
Micron Technology, Inc.
Richardson, TX
We are seeking a Principal Analog Design Engineer to lead the design, integration, and delivery of advanced analog and mixed-signal IPs for High Bandwidth Memory (HBM) products. This role…
Added 15 days ago
Principal Modem SOC Design Engineer - Terawave
Blue Origin Personnel, LLC
Cupertino, CA · San Diego, CA
As a Principal Modem SOC Design Engineer on the ASIC Engineering SOC Team, you will be a technical design leader for the TeraWave satellite communication System on Chip (SOC). This…
Added 15 days ago
Senior Systems Applications Engineer
NXP USA Inc.
United States
You will join a highly experienced team of processor, memory, and system experts responsible for solving challenging customer problems, enabling new technologies, and influencing future SoC…
Added 15 days ago
Senior Embedded Software Engineer
Glydways
CA
Develop and optimize applications in RTOS environments, tuning for reliability, latency, throughput, memory footprint, and power on resource-constrained platforms.
Added 16 days ago
Lead SoC Architect
IntelliPro Group Inc.
Sunnyvale, CA
A semiconductor startup developing next-generation graphics processors is seeking an experienced Lead SoC Architect to own architecture definition and technical direction for advanced…
Added 17 days ago
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Senior Manager, Servo Firmware Engineering
Western Digital
San Jose, CA
- $184,500 to $246,000 USD / year
…Jose, CA or Irvine, CA, United States. In this role, you will lead the US HDD servo firmware development team responsible for the strategic vision and execution of the servo subsystem…
Added 17 days ago
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Principal Avionics Engineer
Parallax Space, Inc.
Denver, CO · Redondo Beach, CA
- $150,000 to $240,000 USD / year
Set processor, FPGA/SoC, memory, redundancy, and fault-tolerance strategies matched to mission class, orbit, and radiation environment.
Added 18 days ago
Director, Engineering, Analog Mixed-Signal
Google
Mountain View, CA
Own the overall Power, Performance, and Area (PPA) envelope for the entire memory subsystem, dictating trade-offs and ensuring DDR access meets the extreme, high-stakes requirements of…
Added 20 days ago
AI Systems Engineer, Hardware Architecture
Meta
Washington, DC
Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads
Added 20 days ago
AI Systems Engineer, Hardware Architecture
Meta
Phoenix, AZ
Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads
Added 20 days ago
AI Systems Engineer, Hardware Architecture
Meta
Hartford, CT
Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads

AI Systems Engineer, Hardware Architecture

Lincoln, NE, United States

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Job details

Experience: 12+ years of experience in hardware systems architecture, with a focus on AI, ML, imaging systems, or high-performance compute systems
Posting language: English
Posted: Oct 23, 2026

Original job description

Summary:

Meta Reality Labs is seeking a principal-level AI Systems Engineer to define the hardware architecture strategy for next-generation AI-accelerated computing systems powering virtual and augmented reality products. In this role, you will shape the long-term silicon and systems roadmap for on-device AI inference and training workloads across wearables, headsets, and spatial computing platforms. A core focus of this role is driving the architecture of advanced imaging systems and camera pipelines that enable real-time perception, scene understanding, and mixed reality experiences. You will drive architectural decisions that span custom silicon, memory subsystems, interconnects, image signal processors (ISPs), camera subsystems, and software-hardware co-design, ensuring Meta's AI hardware remains at the forefront of performance, efficiency, and capability for immersive computing experiences.

Required Skills:

AI Systems Engineer, Hardware Architecture Responsibilities:

Define multi-generation hardware architecture strategy for AI inference and training systems across VR, AR, and wearable device platforms
Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads
Architect end-to-end camera and imaging pipelines, including sensor interfaces, ISP integration, and real-time image processing for computer vision and perception applications
Drive hardware-software co-design initiatives by partnering with silicon engineering, firmware, camera systems, and ML platform teams to optimize end-to-end AI and imaging pipeline performance
Define architectural requirements for camera subsystems including multi-camera synchronization, depth sensing, and low-latency visual processing for AR/VR applications
Establish architectural requirements and performance targets for custom AI accelerators, ISPs, SoCs, and supporting subsystems in spatial computing devices
Develop and maintain system performance models and simulation frameworks to evaluate architectural decisions against real-world AI and imaging workload characteristics
Provide architectural guidance and technical direction across hardware engineering organizations, aligning imaging and AI roadmaps with product and research priorities
Identify and resolve system-level bottlenecks in imaging latency, AI inference throughput, and energy efficiency for wearable and headset form factors
Engage with external silicon partners, camera module vendors, and research institutions to evaluate emerging imaging technologies and incorporate them into long-range architecture plans
Communicate architectural vision and technical rationale to executive leadership and cross-functional stakeholders through written proposals and design reviews

Minimum Qualifications:

12+ years of experience in hardware systems architecture, with a focus on AI, ML, imaging systems, or high-performance compute systems
Deep expertise in camera pipeline architecture, including image signal processing (ISP), sensor integration, and end-to-end imaging system design
Experience defining SoC or system-level architecture for AI inference or training workloads, including memory subsystem design, compute hierarchy, and interconnect topology
Experience architecting imaging subsystems for real-time computer vision applications, including multi-camera systems, depth sensing, and visual-inertial odometry
Experience with hardware-software co-design methodologies for on-device AI and imaging workloads, including familiarity with ML compiler stacks and ISP tuning workflows
Experience developing system performance models and using simulation or analytical frameworks to evaluate architectural trade-offs at scale
Track record of driving multi-year hardware architecture roadmaps for imaging and AI systems and influencing silicon strategy across large engineering organizations

Preferred Qualifications:

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation
Experience architecting AI and imaging systems for power- and area-constrained wearable or mobile devices, including VR headsets, AR glasses, or similar spatial computing platforms
Expertise in computational photography pipelines, HDR processing, and neural ISP architectures
Background in collaborating with ML research and camera teams to translate novel imaging algorithms and model architectures into hardware-efficient deployment targets
Experience evaluating and integrating emerging memory technologies (e.g., HBM, LPDDR5X, in-memory compute) into AI and imaging system architectures

Public Compensation:

$208,000/year to $289,000/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.

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Skills

Firmware
ML
Research
Energy efficiency
Imaging techniques
Signal processing
RTL
Photography

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Work requirements

Jobs in the United States