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Principal Analog Design Engineer

Micron Technology, Inc.

Richardson, TX

We are seeking a Principal Analog Design Engineer to lead the design, integration, and delivery of advanced analog and mixed-signal IPs for High Bandwidth Memory (HBM) products. This role…

Principal Modem SOC Design Engineer - Terawave

Blue Origin Personnel, LLC

Cupertino, CA · San Diego, CA

As a Principal Modem SOC Design Engineer on the ASIC Engineering SOC Team, you will be a technical design leader for the TeraWave satellite communication System on Chip (SOC). This…

Senior Systems Applications Engineer

NXP USA Inc.

United States

You will join a highly experienced team of processor, memory, and system experts responsible for solving challenging customer problems, enabling new technologies, and influencing future SoC…

Senior Embedded Software Engineer

Glydways

Remote, United States

Develop and optimize applications in RTOS environments, tuning for reliability, latency, throughput, memory footprint, and power on resource-constrained platforms.

Lead SoC Architect

IntelliPro Group Inc.

Sunnyvale, CA

A semiconductor startup developing next-generation graphics processors is seeking an experienced Lead SoC Architect to own architecture definition and technical direction for advanced…

Senior Manager, Servo Firmware Engineering

Western Digital

San Jose, CA

• $184,500 to $246,000 USD / year

…Jose, CA or Irvine, CA, United States. In this role, you will lead the US HDD servo firmware development team responsible for the strategic vision and execution of the servo subsystem…

Principal Avionics Engineer

Parallax Space, Inc.

Denver, CO · Redondo Beach, CA

• $150,000 to $240,000 USD / year

Set processor, FPGA/SoC, memory, redundancy, and fault-tolerance strategies matched to mission class, orbit, and radiation environment.

Sr. Electrical Design Engineer III

Actalent

Redmond, WA

• $64.46 USD / hour

Lead digital board bring-up, including power-on procedures, clock initialization, interface configuration, and link validation.

Director, Engineering, Analog Mixed-Signal

Google

Mountain View, CA

Own the overall Power, Performance, and Area (PPA) envelope for the entire memory subsystem, dictating trade-offs and ensuring DDR access meets the extreme, high-stakes requirements of…

AI Systems Engineer, Hardware Architecture

Meta

Washington, DC

Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads

AI Systems Engineer, Hardware Architecture

Meta

Phoenix, AZ

Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads

AI Systems Engineer, Hardware Architecture

Meta

Hartford, CT

Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads

AI Systems Engineer, Hardware Architecture

Meta

Charleston, WV

Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads

AI Systems Engineer, Hardware Architecture

Meta

Richmond, VA

Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads

AI Systems Engineer, Hardware Architecture

Meta

Lansing, MI

Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads

AI Systems Engineer, Hardware Architecture

Meta

Nashville, TN

Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads

AI Systems Engineer, Hardware Architecture

Meta

Santa Fe, NM

Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads

AI Systems Engineer, Hardware Architecture

Meta

Concord, NH

Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads

AI Systems Engineer, Hardware Architecture

Meta

Trenton, NJ

Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads

AI Systems Engineer, Hardware Architecture

Meta

Columbia, SC

Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads

AI Systems Engineer, Hardware Architecture

Meta

Lincoln, NE

Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads

AI Systems Engineer, Hardware Architecture

Meta

Boise, ID

Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads

AI Systems Engineer, Hardware Architecture

Meta

Bismarck, ND

Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads

AI Systems Engineer, Hardware Architecture

Meta

Boston, MA

Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads

AI Systems Engineer, Hardware Architecture

Meta

Pierre, SD

Lead system-level architectural exploration and trade-off analysis across compute, memory hierarchy, interconnect fabric, and power delivery for on-device AI workloads