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Senior PCB Layout and Design Engineer

  • Canoga Park, CA, United States

Level 3 Pay Rate: $66.00 Level 4 Pay Rate: $75.50 **US Citizenship is required.**

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Job details

Pay
Level 3 Pay Rate: $66.00 Level 4 Pay Rate: $75.50 **US Citizenship is required.**
Experience
Typically 7+ years of PCB layout and design experience, including responsibility for complex multilayer boards.
Posting language
English
Posted

Original job description

We have an outstanding Contract position for a Senior PCB Layout and Design Engineer to join a leading Company located in the Canoga Park, CA surrounding area.

Level 3 Pay Rate: $66.00 Level 4 Pay Rate: $75.50 **US Citizenship is required.**

The Senior PCB Layout and Design Engineer leads the physical design and layout of complex printed circuit boards, translating electrical schematics and engineering requirements into manufacturable, reliable PCB designs. This role works closely with electrical, mechanical, manufacturing, and test teams to support product development from concept through production.

Job Responsibilities:

  • Develop layouts for multilayer PCBs incorporating high-speed digital, analog, mixed-signal, RF, and power circuitry, as applicable.
  • Define board stackups, component placement, routing constraints, and fabrication requirements in collaboration with engineering teams and PCB suppliers.
  • Apply signal integrity, power integrity, impedance control, grounding, shielding, and thermal-management principles.
  • Route critical interfaces, including differential pairs, clocks, memory buses, and other timing-sensitive signals.
  • Coordinate electrical and mechanical requirements, including board outlines, connector locations, mounting features, and enclosure clearances.
  • Perform design-rule checks and resolve layout, connectivity, clearance, and manufacturing issues.
  • Conduct design-for-manufacturing, assembly, and test reviews with fabrication, assembly, and test partners.
  • Generate and maintain manufacturing deliverables, including fabrication and assembly drawings, drill files, Gerber or ODB++ data, and pick-and-place files.
  • Manage layout revisions, engineering changes, design documentation, and release activities.
  • Support prototype bring-up, troubleshooting, and resolution of board-level performance or manufacturing issues.
  • Lead PCB design reviews, mentor junior designers, and improve design standards, libraries, and workflows.

Basic Hiring Criteria:

  • Bachelor's degree in electrical engineering, electronics engineering, or a related field, or equivalent relevant education and experience.
  • Typically 7+ years of PCB layout and design experience, including responsibility for complex multilayer boards.
  • Proficiency with Altium Designer PCB design platform.
  • Strong understanding of PCB fabrication and assembly processes, material selection, stackup development, and component packaging.
  • Demonstrated experience with controlled-impedance routing, differential pairs, length matching, and high-density component placement.
  • Ability to interpret electrical schematics, component datasheets, interface requirements, and mechanical drawings.
  • Working knowledge of relevant IPC standards, such as IPC-2221, IPC-2222, IPC-7351, and IPC-6012, as applicable to the product.
  • Experience with design-rule checking, manufacturing documentation, revision control, and configuration-management processes.
  • Strong communication, problem-solving, and cross-functional collaboration skills.
  • Ability to manage competing priorities and deliver designs within project schedules.

Desired Qualifications:

  • Proficiency with Altium, OrCAD Designer PCB design platform, knowledge of Mentor Graphics BoardStation.
  • Proficiency with Windchill Product Lifecycle Management (PLM)
  • Experience with High-Density Interconnect (HDI) designs, microvias, blind/buried vias, fine-pitch BGAs, and rigid-flex or flex circuits.
  • Experience laying out interfaces such as DDR, PCIe, Ethernet, USB, and other high-speed communication buses.
  • Familiarity with signal- and power-integrity analysis tools and the ability to incorporate simulation results into layout.
  • Experience designing for EMI/EMC performance and environmental or reliability requirements.
  • IPC Certified Interconnect Designer certification, CID or CID+.
  • Experience in aerospace, defense, medical, automotive, or other high-reliability industries.
  • Experience developing CAD libraries, validating footprints, and maintaining enterprise design rules.

Benefits offered vary by contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, and affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.

Military connected talent encouraged to apply.

VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled

To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit http://www.tadpgs.com/candidate-privacy/ or https://pdsdefense.com/candidate-privacy/

The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:

  • The California Fair Chance Act
  • Los Angeles City Fair Chance Ordinance
  • Los Angeles County Fair Chance Ordinance for Employers
  • San Francisco Fair Chance Ordinance

Military connected talent encouraged to apply.

VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled

To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit http://www.tadpgs.com/candidate-privacy/ or https://pdsdefense.com/candidate-privacy/

The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:

  • The California Fair Chance Act
  • Los Angeles City Fair Chance Ordinance
  • Los Angeles County Fair Chance Ordinance for Employers
  • San Francisco Fair Chance Ordinance
More about this job

Skills

  • Printed circuit boards
  • Assembly
  • Documentation
  • Troubleshooting
  • Electrical engineering
  • Altium Designer
  • Packaging
  • Technical drawings
  • IPC standards
  • Communication skills
  • Problem solving
  • Collaboration
  • Mentor Graphics
  • PTC Windchill
  • PLM
  • EMI
  • Counselling

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