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Added 7 mins ago
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Lead Principal Platform Software Engineer
Oracle
Nashville, TN
- $113,600 to $306,400 USD / year
We are seeking a Lead Principal Software Engineer to set long-term technical direction for the Robotics Automation Platform. You will lead architecture and technical delivery across…
Added 7 mins ago
O
Senior Platform Software Engineer
Oracle
Nashville, TN
- $87,800 to $209,500 USD / year
Software Engineer - OCI User Experience Engineering Platform
Added 57 mins ago
Avionics Test Engineer I- Onsite
RTX Corporation
annapolis, MD
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Added 1 hour ago
Intern, Electrical Engineering
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United States
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Added 3 hours ago
O
Lead Principal Software Engineer, Core Infrastructure
Oracle
Nashville, TN
- $146,300 to $306,400 USD / year
As a Consulting Member of Technical Staff, you will own the software design and development for major components of Oracle's Cloud Infrastructure. You should be both a rock-solid lead…
Added 3 hours ago
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Lead Principal Platform Software Engineer
Oracle
Seattle, WA · Santa Clara, CA
- $113,600 to $306,400 USD / year
We are seeking a Lead Principal Platform Software Engineer to lead the architecture and delivery of critical platform systems and initiatives across teams. This is a hands-on technical…
Added 4 hours ago
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Staff Engineer, Process Control & Data Solutions
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Charlotte, NC
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Austin, TX
The Security Platform Engineer owns the reusable platform capabilities that embed security and compliance into our development and delivery workflows. You will build and run the security…
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Senior Electronics Engineer
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Moon Township, PA
- $86,000 to $126,000 USD / year
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Added 4 hours ago
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Robotics Software Engineer
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Watertown, MA
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Added 5 hours ago
Security Engineer
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United States
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Electronics Engineer II (Advanced Electronics Systems and Technologies | 345C)
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Pasadena, CA
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Electronics Engineer I (Advanced Electronics Systems and Technologies | 345C)
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Principal Design Quality & Reliability Engineer - OCI Data Center Infrastructure
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Jefferson City, MO
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Staff DevOps Engineer
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Experience in software testing and/or test automation, including independently writing test cases and automated tests, and developing or executing test documentation.
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Senior Security Engineer - Secure SDLC
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Highmark Health is seeking a Senior Security Engineer to join our Enterprise Application Security team and play a pivotal role in shaping how security is built into our software - not…
Added 5 hours ago
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Software Engineer Intern, Software Platforms & Product [Summer 2027]
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Foster City, CA
- $6,500 to $9,500 USD / month
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Added 5 hours ago
Embedded Software Engineer IV
Wabtec
Germantown, MD
As an Embedded Software Engineer, you will collaborate with cross-functional engineering teams to design, develop, and maintain embedded software solutions for industrial electronics…
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Senior DevOps Mobile Operations Engineer
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Plano, TX
Our client, Medical Device Software & Connected Systems is seeking a Senior DevOps Mobile Operations Engineer to join their team. As a Senior DevOps Mobile Operations Engineer, you will be…
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Added 6 hours ago
Senior Software Engineer, Project Leo Customer Terminals
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Austin, TX
In this role, you will develop software for the Leo Customer Terminal embedded systems engineering team. You will be responsible for the design, implementation, deployment and operations of…
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Senior Software Engineer, Project Leo Customer Terminals
Amazon
Austin, TX
In this role, you will develop software for the Leo Customer Terminal embedded systems engineering team. You will be responsible for the design, implementation, deployment and operations of…

Synopsys

SOC Engineering, Principal Engineer

Austin, TX, United States

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Job details

Experience: 15+ years of ASIC/SoC design verification experience, including hands-on subsystem or full-chip ownership through multiple tape-outs.
Posting language: English
Posted: Nov 5, 2026

Original job description

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are You are a hands-on verification leader who translates complex architectural and system requirements into executable verification plans and measurable sign-off criteria. You understand that the hardest integration bugs often emerge from interactions between processors, interconnects, memory, firmware, and system-control logic.

You combine technical leadership with practical execution. You can architect a UVM environment, debug a processor boot failure, investigate an interrupt or power-sequencing issue, and guide engineers through coverage closure. You distinguish RTL defects from testbench, software, configuration, and specification issues, and drive them toward resolution.

You lead with clear priorities and technical credibility. You work directly with customers and cross-functional teams, communicate risks early, and make evidence-based readiness decisions. Your architectural understanding and reusable verification skills allow you to contribute across different subsystem functions and full-chip engagements.

What You’ll Be Doing

Lead subsystem and SoC verification from requirements review and planning through environment development, regression execution, coverage closure, and sign-off.
Translate specifications into verification plans, test scenarios, coverage models, checkers, and traceable acceptance criteria.
Architect reusable SystemVerilog/UVM environments integrating commercial VIP, processor models, register models, assertions, reference models, and scoreboards.
Verify processor and system integration, including boot flows, address mapping, memory access, coherency, interrupts, timers, debug, and configuration interfaces.
Drive verification of clock switching and gating, reset sequencing, power-state transitions, isolation, retention, and cross-domain dependencies.
Verify fault-management and recovery behavior, including error capture, masking, aggregation, ECC/parity, watchdogs, monitors, and error injection.
Develop directed, constrained-random, and embedded C tests covering concurrent traffic, corner cases, initialization, and failure/recovery sequences.
Lead root-cause debug across RTL, verification environments, firmware, and third-party IP; coordinate fixes and verify resolution.
Own regression health, defect tracking, requirements traceability, functional/code coverage, milestone readiness, and sign-off evidence.
Mentor engineers and coordinate technical execution with architecture, design, firmware, formal verification, and other engineering teams.

The Impact You Will Have

Identify critical integration and system-level defects before silicon, improving quality and reducing late-stage program risk.
Establish clear verification scope and measurable closure criteria that support predictable customer milestones.
Build reusable environments and methodologies that accelerate future subsystem and SoC engagements.
Improve execution efficiency through effective debug, automation, disciplined regressions, and risk-based prioritization.
Strengthen customer confidence through transparent communication and traceable verification evidence.
Develop engineers into independent technical owners and future verification leaders.

What You’ll Need

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
15+ years of ASIC/SoC design verification experience, including hands-on subsystem or full-chip ownership through multiple tape-outs.
Proven experience leading verification teams and driving technical execution through major milestones and sign-off.
Strong SystemVerilog/UVM expertise, including constrained-random stimulus, assertions, functional coverage, scoreboards, and register models.
Deep understanding of processor-based SoC architectures, including multicore integration, memory hierarchy, coherent interconnects, interrupts, boot, and debug.
Hands-on experience verifying clock, reset, and power-control logic, including sequencing, state transitions, dependencies, and recovery behavior.
Experience verifying hardware fault-management mechanisms, including error reporting, masking, ECC/parity, error injection, and fault recovery.
Working knowledge of AMBA interfaces and coherent interconnect protocols, with practical system-level transaction-debug experience.
Embedded C/C++ experience for initialization, processor-driven tests, interrupt handling, and hardware/software debug.
Strong capability in regression management, coverage analysis, requirements traceability, and verification closure.
Experience with simulation, waveform-debug, and verification-management tools, plus scripting in Python, Tcl, or shell.
Strong communication skills and experience working with customers and geographically distributed teams.

Preferred Qualifications

Low-power verification using UPF and power-aware simulation.
Lockstep verification and requirements-based verification for safety-critical designs.
Formal verification and assertion-based verification experience.
Emulation experience, including platform bring-up, software-driven testing, or simulation-to-emulation test reuse, is a plus.
Experience with Synopsys VCS, Verdi, VC Formal, and verification-management tools.

Who You Are

You identify missing scenarios in a verification plan and explain the resulting product risk.
You move comfortably between technical planning, environment reviews, and hands-on debug.
You challenge ambiguous requirements constructively and establish agreement on expected behavior.
You give engineers clear ownership while remaining accountable for integration and delivery.
You assess readiness using passing tests, coverage, and defect evidence rather than activity alone.
You make sound sign-off recommendations under schedule pressure and communicate unresolved risks clearly.

The Team You’ll Be Part Of You will join the Synopsys Solutions group, delivering end-to-end SoC and subsystem engineering services across diverse customer programs. You will collaborate with architecture, RTL design, firmware, verification, DFT, and physical design teams. Your responsibilities may span different subsystem functions and full-chip engagements, providing opportunities to apply your technical leadership across architectures and markets.

Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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