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Community Engagement Manager
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Synopsys

Digital CAD DFT Methodology, Sr Architect-19503

Sunnyvale, CA, United States

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Job details

Experience: 18+ years of experience in the semiconductor or EDA industry, including deep experience in DFT, ATPG, and manufacturing test methodologies
Posting language: English
Posted: Nov 5, 2026

Original job description

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You are a senior DFT architect with deep experience developing and deploying test solutions for complex ASIC and SoC designs. You bring strong expertise in scan architectures, ATPG, test access infrastructures, and DFT standards, along with the judgment to guide technical direction across complex programs and customer engagements. You have a track record of solving difficult technical challenges, advancing methodology adoption, and helping teams deliver scalable, production-ready test solutions. You are comfortable working across design, product, and applications teams, and you know how to translate deep technical expertise into practical customer and business outcomes. Position can be in the following locations: California, Texas or Oregon What You’ll Be Doing

Drive advanced DFT methodologies for complex ASIC and SoC programs across customer and internal engagements
Serve as a senior technical expert for Synopsys TestMAX DFT, ATPG, diagnosis, and silicon lifecycle solutions
Lead deployment of advanced DFT architectures including scan compression, hierarchical DFT, boundary scan, IEEE 1500 wrapper solutions, IJTAG infrastructures, and embedded test technologies
Architect scalable test access and instrumentation networks using IEEE 1149.1, IEEE 1149.6, IEEE 1687, and IEEE 1500 standards
Develop best practices for DFT insertion, ATPG generation, pattern validation, diagnosis, and coverage optimization
Drive reusable methodologies, automation, and signoff criteria that improve deployment quality and engineering efficiency
Partner with R&D teams to influence product capabilities and methodology improvements
Support strategic customer engagements, methodology reviews, and complex technical escalations
Mentor engineers and help strengthen DFT expertise across the organization

The Impact You Will Have

Enable successful deployment of advanced DFT methodologies across some of the most complex semiconductor programs in the industry
Improve test quality, manufacturability, and silicon reliability for strategic customers
Influence TestMAX methodology adoption through technical leadership and trusted customer engagement
Accelerate use of standards-based test architecture across key customer accounts
Improve engineering productivity through automation, methodology standardization, and best-practice development
Strengthen Synopsys’ position as a trusted partner in DFT and manufacturing test solutions
Contribute to technologies powering AI, automotive, networking, and high-performance computing applications

What You’ll Need

BS/MS in Electrical Engineering, Computer Engineering, or a related field
18+ years of experience in the semiconductor or EDA industry, including deep experience in DFT, ATPG, and manufacturing test methodologies
Demonstrated expertise in architecting and implementing DFT solutions for large-scale ASIC and SoC designs
Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions
Strong understanding of scan insertion, scan compression, hierarchical DFT, ATPG, diagnosis, coverage optimization, and test cost reduction techniques
Expertise with standards including IEEE 1149.1, IEEE 1149.6, IEEE 1687, and IEEE 1500
Experience developing and deploying JTAG / TAP architectures, boundary scan networks, IJTAG instrumentation networks, and embedded instrument access solutions
Expertise integrating DFT IP including embedded compression, OCC, LBIST, TAP controllers, JTAG / IJTAG infrastructure, TDR networks, and IEEE 1500 wrappers
Strong understanding of RTL-to-GDSII implementation flows and the interaction between DFT, synthesis, physical design, timing closure, and signoff
Proficiency in Tcl, Python, Perl, Shell, or similar scripting languages for methodology development and automation

Who You Are

A strategic and trusted technical leader capable of influencing engineering direction across organizations and supporting our customers, partners and internal stakeholders.
An exceptional communicator who can present complex technical concepts to diverse audiences.
A mentor and innovator; someone who develops talent and always seeking opportunities to improve methodologies, tools and customer outcomes
Results-driven, highly collaborative, and passionate about solving the industry's most challenging DFT problems.

The Team You'll Be A Part Of You will join the Digital Methodology Center of Excellence, a highly visible organization responsible for defining and advancing Synopsys' DFT methodologies, best practices, and customer deployment strategies. Working closely with R&D, product engineering, customer success, and strategic accounts, you will help shape the future of Design-for-Test and drive successful adoption of the industry's most advanced test solutions worldwide.

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