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Added 13 hours ago
ASIC Design Engineer
Microchip - USA
CA
Join the Design Engineering team as Technical Staff Engineer-Design supporting semiconductor architecture, RTL and circuit design, integration, verification, performance, power, area,…
Added 13 hours ago
Digital Failure Analysis Engineer (Dallas/Richardson)
Texas Instruments
Richardson, TX
Experience in DFT and ATPG for SoC or ASIC designs
Added 16 hours ago
DFT Engineer
Broadcom Corporation
United States
Broadcom's ASIC Product Division is seeking candidates for a DFT Engineer position at our San Jose, California Development Center. The successful candidate will participate in SoC DFT…
Added 16 hours ago
ASIC DFT Engineer
Broadcom Corporation
United States
Broadcom's ASIC Product Division is seeking candidates for a DFT Engineer position at our San Jose, California Development Center. The successful candidate will participate in SoC DFT…
Added 16 hours ago
ATE Engineer - XPU (Yield, Quality & RMA)
Broadcom Corporation
United States
ATE Test Engineer – XPU Yield, Quality, and RMA Debug
Added 16 hours ago
ATE Engineer - XPU (Yield, Quality & RMA)
Broadcom Corporation
United States
ATE Test Engineer – XPU Yield, Quality, and RMA Debug
Added 16 hours ago
ASIC DFT Engineer
Broadcom Corporation
United States
Broadcom's ASIC Product Division is seeking candidates for a DFT Engineer position at our San Jose, California Development Center. The successful candidate will participate in SoC DFT…
Added 21 hours ago
A
Principal ASIC Design Engineer
Aerospace
Plymouth, MN · Clearwater, FL
- $173,000 to $200,000 USD / year
As a Principal ASIC Design Engineer at Honeywell Aerospace, you will be a technical leader in our ASIC design team, responsible for driving innovation and excellence in ASIC design, leading…
Added 1 day ago
Physical Design Engineer
Inabia Software & Consulting Inc.
San Jose, CA
Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.
Added 1 day ago
Design/SDC Engineer
Inabia Software & Consulting Inc.
San Jose, CA
You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in…
Added 2 days ago
M
Principal Design Engineer
Microsoft
NC · CA · Raleigh, NC · Mountain View, CA · Raleigh · Mountain View
- $142,800 to $304,200 USD / year
We are looking for a Principal Design Engineer to join the team.
Added 2 days ago
ASIC Test Development Engineer
Cisco Systems, Inc.
San Jose, CA
As our next ASIC Test Development Engineer in Silicon Operations, you are the backbone of our ATE test bring-up process. You will collaborate with ASIC design teams in the Central Hardware…
Added 2 days ago
C
ASIC DFT Engineer I (Full Time) - United States
Cisco
San Jose, CA · RTP, NC · Allentown, PA
- Full-time
You will be in the Silicon One development organization as an ASIC Design for Test Engineer with a primary focus on Design-for-Test. You will work with frontend RTL teams, backend Physical…
Added 2 days ago
PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning
Amazon
Cupertino, CA
…integration of emergent technologies. We’re looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring high design…
Added 3 days ago
DFT Engineer
LSI Corporation
United States
Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose. California Development Center. The successful candidate will work on DFT programs all the way from…
Added 3 days ago
DFT Engineer
LSI Corporation
United States
Broadcom's ASIC Product Division is seeking candidates for a DFT position at our Austin, Texas Development Center. The successful candidate will work on DFT programs all the way from chip…
Added 3 days ago
Sr/Staff Digital Design Engineer
Lightmatter
Boston, MA
We are hiring a Digital Design Engineer to help develop an ASIC for the next-generation artificial intelligence computing architecture alongside a team of world-class scientists and…
Added 3 days ago
Sr/Staff Digital Design Engineer
Lightmatter
Mountain View, CA
We are hiring a Digital Design Engineer to help develop an ASIC for the next-generation artificial intelligence computing architecture alongside a team of world-class scientists and…
Added 3 days ago
DFT Lead Engineer
LSI Corporation
United States
Broadcom's ASIC Product Division is seeking candidates for a DFT position at our Austin, Texas Development Center. The successful candidate will be responsible for leading DFT programs all…
Added 3 days ago
DFT Engineer
LSI Corporation
United States
Broadcom's ASIC Product Division is seeking candidates for a DFT position at our Austin, Texas Development Center. The successful candidate will work on DFT programs all the way from chip…
Added 3 days ago
DFT Engineer
LSI Corporation
United States
Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose, California Development Center. The successful candidate will work on DFT programs all the way from…
Added 3 days ago
MTS Silicon Design Engineer
Advanced Micro Devices, Inc
San Jose, CA
Job Role and Responsibility: Xilinx, Inc., a subsidiary of AMD, Inc., is hiring MTS Silicon Design Engineer to Research, design, develop, and/or test electronic components and systems for…
Added 3 days ago
Sr. Silicon Design Engineer
Advanced Micro Devices, Inc
Santa Clara, CA
Job Role and Responsibility: AMD, Inc. is hiring a Sr. Silicon Design Engineer to Research, design, develop, and/or test electronic components and systems for semiconductor and related…
Added 3 days ago
SMTS Silicon Design Engineer
Advanced Micro Devices, Inc
Santa Clara, CA
Job Role and Responsibility: AMD, Inc., is hiring SMTS Silicon Design Engineer to contribute to AMD’s CDFX DV team to perform the DFT IP verification, which includes work on IP level test…
Added 3 days ago
DFT Engineer
Tenstorrent
Austin, TX · Fort Collins, CO · Santa Clara, CA
The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation…

Closed listing

SpaceX

Sr. SOC Physical Verification Engineer (Silicon Engineering)

Palo Alto, CA, United States
Austin, TX, United States
Irvine, CA, United States
Sunnyvale, CA, United States

This opening has closed.

The original listing is kept below for reference.

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About employer

Job details

Experience: 5+ years of ASIC and/or physical design flow development experience in industry
Posting language: English
Posted: Oct 26, 2026

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Original job description

Archived listing. The details below describe a past opening.

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

SR. SOC PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES:

Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus
Develop, maintain, and optimize physical verification flows for advanced node SoC’s.
Interpret and implement foundry Design Rule Manuals (DRM) - translate rule updates into verified flow changes
Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance
Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams
Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements.Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows

BASIC QUALIFICATIONS:

Bachelor’s degree in electrical engineering, computer engineering or computer science
5+ years of ASIC and/or physical design flow development experience in industry

PREFERRED SKILLS AND EXPERIENCE:

Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation)

• Experience in IP integration (e.g. memories, I/O’s, analog IPs, SerDes, DDR etc.)

Deep expertise in DRC, LVS, PERC and ESD verification methodologies
Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus
Direct foundry DRM experience - able to read, interpret, and implement complex rule decks
Experience at advanced nodes (4nm and below)
Experience with large SOC designs (>10M gates) with frequencies in excess of 1GHZ
Excellent scripting skills (csh/bash, Perl, Python TCL, Makefile etc.)
Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:

Ability to work extended hours and weekends as needed to meet critical project milestones

COMPENSATION AND BENEFITS:

Pay range:

Physical Design Engineer/Senior: $175,000.00 - $280,000.00/per year

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

ITAR REQUIREMENTS:

To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.

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Skills

Regulatory compliance
Reporting
BASIC
Electrical engineering
Computer engineering
Computer science
DFT
Perl
Python

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