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Semtech Photonics

Sr. Engineer, Process Development

City of Industry, CA, United States

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Job details

Education: Master’s degree
Posting language: English
Posted: Oct 28, 2026

Original job description

Location: Rowland, CA (Onsite)

Position Summary The Process Engineer is responsible for developing, optimizing, and sustaining wafer fabrication processes that support yield, quality, and throughput for InP photonic device lines, specifically InP Buried Heterostructure (BH) DFB lasers and BH Gain Chips (GC). The Process Engineer owns one or more fab process modules (photolithography, PECVD, dry etch, wet etch, and metallization), including the Mesa etch and surface preparation steps that support MOCVD epitaxial regrowth of InP current-blocking layers used to form the buried heterostructure. This role applies advanced technical training in materials, semiconductor processing, and statistical methods to resolve process excursions, improve device performance and yield, and transition new processes into volume production.

Working in a III-V cleanroom environment with minimal supervision, the Process Engineer partners closely with Wafer Fab Supervisors, Technicians, Equipment Engineering, Device and Test Engineering, and Quality to maintain Process-of-Record (POR) discipline, drive data-based decisions, and support reliable, high-yield, high-volume manufacturing.

Responsibilities:

Process Development & Module Ownership

Own assigned process modules (photolithography, PECVD, dry etch, wet etch, and/or metallization) for InP BH DFB laser and BH GC production, with responsibility for process capability, stability, and yield performance
Develop, characterize, and optimize processes such as lithography CD and overlay control, dielectric film properties, Mesa etch profile and depth control, surface preparation for MOCVD regrowth, and ohmic contact formation
Define process windows, specifications, and control limits using designed experiments and statistical analysis
Evaluate new materials, chemistries, equipment, and process techniques to improve device performance, yield, throughput, and cost
Characterize process results using SEM, profilometry, ellipsometry, TLM, and device electrical and optical test data to link process parameters to device performance

Excursion Response, Root Cause & Yield Improvement

Lead root-cause investigation and corrective action for process excursions, yield loss, and drift (e.g., CD shift, film stress or thickness non-uniformity, etch rate or profile drift, contact resistance shift)
Analyze in-line, wafer-level, and device-level data to identify yield detractors and prioritize improvement projects
Use structured problem-solving methods (8D, fishbone, FMEA) and short-loop experiments to isolate root cause and verify corrective actions
Work with Equipment Engineering to resolve tool-related issues and to qualify tools after maintenance or modification

Process Control, Documentation & Change Management

Define and review SPC charts, control limits, and monitor strategies for assigned process modules, and ensure out-of-control events are addressed in a timely manner
Author and maintain POR documentation, process specifications, and work instructions for assigned process areas
Approve and manage process changes through the change control system, including qualification and post-change verification of process stability
Provide technical guidance, training, and process-specific direction to Wafer Fab Supervisors, Technicians, and Operators

NPI, DOE & Cross-Functional Support

Plan and execute DOEs, process qualifications, and NPI process runs, and transition new or modified processes into volume production
Partner with Device Engineering, MOCVD/Epitaxy, Test, Quality, and Production Planning to align process capability with product requirements and customer commitments
Prepare technical reports, data summaries, and presentations for fab management and cross-functional teams
Support customer and supplier technical reviews, audits, and failure analysis activities as needed

Minimum Qualifications:

Master’s degree in materials science, electrical engineering, chemical engineering, physics, or a related engineering or science field required
2 - 5 years of experience in semiconductor/photonics wafer processing, with direct III-V/InP process experience preferred; relevant graduate research in III-V device fabrication will be considered toward experience
Hands-on experience with one or more of the following process areas: photolithography, PECVD, dry etch, wet etch, and metallization
Experience with InP-based laser or photonic integrated circuit fabrication preferred
Strong working knowledge of semiconductor process physics and chemistry, including lithography, thin film deposition, plasma and wet etch, and metallization/ohmic contact formation for III-V materials
Proficiency in statistical analysis, SPC, and design of experiments (DOE) using tools such as JMP, Minitab, Python, or equivalent
Demonstrated ability to independently lead root-cause investigations and drive corrective actions to closure
Ability to correlate process data with device electrical and optical performance
Familiarity with fab metrology and characterization tools (CD-SEM, profilometer, ellipsometer, XRD, SEM, TLM test structures)
Strong written and verbal communication skills, with the ability to present technical results to management and cross-functional teams
Ability to work effectively with technicians, supervisors, and engineers in a team environment
Ability to work in a cleanroom environment for extended periods across multiple process bays
Ability to work around chemicals (acids, solvents), process gases, and precious metals with proper safety procedures
May require flexibility to support engineering runs or excursions outside standard shift hours

The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description.

All duties and responsibilities are essential job functions and requirements and are subject to possible modification to reasonably accommodate individuals with disabilities.

A reasonable estimate of the pay range for this position is $95,000 – $135,000. There are several factors taken into consideration in determining base salary, including but not limited to: job-related qualifications, skills, education and experience, as well as job location and the value of other elements of an employee’s total compensation package.

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