Jobs in the United States

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Added 47 mins ago
Engineer/Principal Engineer Systems-17346
CORP-Corporate Office
United States
The Mission Defense Team (MDT) is seeking a highly motivated and qualified system engineer to serve as a Hardware Assurance Engineer. You will be responsible for assessing and prioritizing…
Added 47 mins ago
Systems Engineer -20539
CORP-Corporate Office
United States
The Mission Defense Team (MDT) is seeking a highly motivated and qualified system engineer to serve as a Hardware Assurance Engineer, Level 2. You will be responsible for assessing and…
Added 47 mins ago
Principal/Sr Principal Engineer Systems-17345
CORP-Corporate Office
United States
The Mission Defense Team (MDT) is seeking a highly motivated and qualified system engineer to serve as a Hardware Assurance Engineer. You will be responsible for assessing and prioritizing…
Added 1 hour ago
VLSI Physical Design Lead Engineer
Hewlett Packard Enterprise
Ft. Collins, CO · Chippewa Falls, WI · Bloomington, MN
Experience developing ASIC implementation flows, automation, and design methodologies.
Added 1 hour ago
VLSI Physical Design Engineer
Hewlett Packard Enterprise
Ft. Collins, CO · Chippewa Falls, WI · Bloomington, MN
This position provides an opportunity to contribute to the development of sophisticated ASIC products while partnering with experts across architecture, design, physical implementation,…
Added 1 hour ago
Engineer II - Physical Design
Microchip - USA
Chandler, AZ
Join the Physical Design team as a Engineer II-Physical Design supporting semiconductor synthesis, floorplanning, placement, clocking, routing, timing, power, physical verification,…
Added 2 hours ago
M-
Principal Engineer
MSI - (Marvell Semiconductor Inc.) US
Santa Clara, CA
- $290,000 to $330,000 USD / year
Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual…
Added 2 hours ago
M-
Principal Engineer, Design Verification
MSI - (Marvell Semiconductor Inc.) US
Santa Clara, CA
- $238,000 to $248,000 USD / year
ASIC development process, tools and methodologies.
Added 5 hours ago
Static Timing Analysis Engineer
Quest Global
San Jose, CA
Knowledge of clock tree planning and implementation for SoCs.
Added 5 hours ago
Principal FPGA Emulation Engineer
Renesas Electronics
Austin, TX
Extensive FPGA design and implementation experience (typically 10+ years), including a track record of FPGA prototyping or emulation of ASIC/SoC designs.
Added 7 hours ago
Lead ASIC Design Verification Engineer
Chelsea Search Group
Minneapolis, MN
A Lead ASIC Design Verification Engineer will establish, staff, and lead our ASIC verification team. This is a hands-on technical leadership role – you will personally architect and build…
Added 7 hours ago
Lead Design Verification Engineer
Chelsea Search Group
Minneapolis, MN
A Lead ASIC Design Verification Engineer will establish, staff, and lead our ASIC verification team. This is a hands-on technical leadership role – you will personally architect and build…
Added 7 hours ago
Lead UVM Design Verification Engineer
Chelsea Search Group
Minneapolis, MN
A Lead ASIC Design Verification Engineer will establish, staff, and lead our ASIC verification team. This is a hands-on technical leadership role – you will personally architect and build…
Added 8 hours ago
Software Engineer
MONTROSE ENVIRONMENTAL GROUP
SALT LAKE CITY, UT
Added 9 hours ago
Sr AI/ML Performance Architect
SanDisk
Milpitas, CA
In this AI/ML HBF ASIC Performance Modeling position, you will develop high-performance simulation models and modeling methodologies for Sandisk’s next-generation High Bandwidth Flash (HBF)…
Added 19 hours ago
Wireless SOC Verification Engineer
Apple
Sunnyvale, CA
Proven track record of working full ASIC cycle from concept to tape-out to bring-up, including test-planning, testbench implementation, test sequence creation and debugging, and coverage…
Added 19 hours ago
Wireless SOC Verification Engineer
Apple
Irvine, CA
Proven track record of working full ASIC cycle from concept to tape-out to bring-up, including test-planning, testbench implementation, test sequence creation and debugging, and coverage…
Added 19 hours ago
Wireless SOC Verification Engineer
Apple
San Diego, CA
Proven track record of working full ASIC cycle from concept to tape-out to bring-up, including test-planning, testbench implementation, test sequence creation and debugging, and coverage…
Added 22 hours ago
LC
R&D Engineer IC Design
LSI Corporation
Fort Collins, CO
- $182,160 to $183,000 USD / year
Work on Design Implementation activities related to complex digital and mixed signal IP blocks used in the development of Broadcom’s ASIC / SoC products. Activities include constraints…
Added 1 day ago
IG
Systems Engineer Level 4/5
Insight Global
El Segundo, CA
- From $102 USD / hour
We are seeking a Senior/Lead DSP Algorithms Engineer to support the design and development of advanced satellite communications systems for defense, intelligence, and space programs. This…
Added 1 day ago
Technical Program Manager
Unconventional, Inc.
Mountain View, CA
As a Member of Technical Staff, Digital Design Engineer, you will be a foundational member of our small, multi-disciplinary R&D team. We are looking for accomplished and highly motivated…
Added 1 day ago
IG
Embedded Software Engineer
Insight Global
Simi Valley, CA
- From $82 USD / hour
This engineer will develop embedded C/C++ software, bring up new hardware platforms from scratch, develop and adapt board support packages (BSPs) and device drivers, and integrate software…
Added 1 day ago
Senior Specialist, Electrical Engineer- FPGA
L3Harris Technologies
Rochester, NY
Job Title: Sr Specialist, Electrical Engineer- FPGA **Guaranteed Sign-On Bonus**
Added 1 day ago
Specialist Electrical Engineer- FPGA
L3Harris Technologies
Rochester, NY
Job Title: Specialist, Electrical Engineer- FPGA- **Guaranteed Sign-On Bonus**
Added 1 day ago
Principal Wireless Communication Systems Design Engineer
Persistent Systems
New York, NY
Persistent Systems is seeking a Principal Wireless Communication Systems Design Engineer to join our team and be based in our NYC headquarters. In this role, you will be part of a…

Quest Global

Static Timing Analysis Engineer

San Jose, CA, United States

Pay Range: $160,000 - $220,000

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Job details

Pay: Pay Range: $160,000 - $220,000
Posting language: English
Posted: Oct 29, 2026

Original job description

Job Requirements

Who We Are:

Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals and their areas of expertise, we are able to solve problems better, faster. This multi-dimensional approach enables us to solve the most critical and large-scale challenges across the aerospace & defense, automotive, energy, hi-tech, healthcare, medical devices, rail and semiconductor industries. We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we’re eager to hear from you. The achievers and courageous challenge-crushers we seek, have the following characteristics and skills

What You will Do:

Develop and validate timing constraints for intricate SoC designs.
Expertise in Synthesis, Equivalency Checking and STA
Must have Block Level and Multi-voltage Timing Closure experience. Top Level Timing Closure experience a plus.
Experience with Synopsys Tools – Synopsys DC/FC for Synthesis, Synopsys Formality for Equivalency Checking and Synopsys PrimeTime for STA
Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
Conduct pre-route timing checks and quality of results (QoR) analysis.
Automate timing analysis processes using scripting languages such as Tcl or Perl.
Provide guidance on clock tree synthesis and optimization for energy-efficient designs.
Ensure compliance with timing signoff checklists and criteria.

What You Will Bring:

Experience with high-complexity silicon in advanced technology nodes.
Familiarity with timing constraint development for hierarchical designs.
Knowledge of clock tree planning and implementation for SoCs.
Experience with timing ECO creation and final timing signoff.
Proficiency in using STA tools (e.g., PrimeTime, TCM, Tempus) and scripting languages (e.g., Tcl, Perl).
Proficiency in using synthesis tools (Genus)
Must have Full Chip (Top Level) and Block Level and Multi-voltage Timing Closure experience.
Debug and Fix Timing Issues
This STA engineer needs to do Synthesis, Equivalency Checking and STA
Good understanding of Timing Constraints, Exceptions, CTS and clock constraints, Multi-Mode Multi-Corner timing closure expertise.
Synopsys Tools – Synopsys DC/FC for Synthesis, Synopsys Formality for Equivalency Checking and Synopsys PrimeTime for STA
Strong understanding of ASIC design flows, including RTL and place-and-route.
Excellent problem-solving skills and attention to detail.
Effective communication and teamwork abilities.
Bachelors and 8+ years of related experience; at this level post-graduate coursework may be desirable or Masters degree and 6+ years of related experience or PhD and 3+ years of related experience

•

Pay Range: $160,000 - $220,000

Work Requirements:

This role is considered an on-site position located in San Jose /Irvine / San Diego in California

You must be able to commute to and from the location with your own transportation arrangements to meet the required working hours.

Benefits

Full-time (Regular)

401(k)
Dental insurance
Health insurance
Life insurance
Paid time off
Referral program
Vision insurance
Short/Long Term Disability

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