Design Verification Engineer

Overview

• Prodapt is a global technology company and the largest specialized player in the Connectedness industry. As an AI-first strategic partner, Prodapt provides consulting, business transformation, and managed services to top telecom and tech enterprises. Prodapt ASIC Services is a leading provider of SoC ASIC/FPGA and Embedded Software services. We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded services include firmware, device drivers, RTOS porting, and board bring-up. A “Great Place To Work® Certified™” company, Prodapt employs over 6,000 technology and domain experts in 30+ countries. Prodapt is part of the 130-year-old business conglomerate The Jhaver Group, which employs over 32,000 people across 80+ locations globally.

We are seeking an experienced Senior Emulation/Verification Engineer with expertise in simulation acceleration, hardware emulation, and SystemVerilog/UVM-based verification environments in Austin, Texas. The ideal candidate will have strong experience with Cadence Palladium and/or Synopsys ZeBu, enabling efficient pre-silicon verification and accelerating complex SoC validation.

Responsibilities

Key Responsibilities

• Maintain and optimize simulation acceleration and emulation environments using Cadence Palladium and/or Synopsys ZeBu
• Port SystemVerilog/UVM verification environments to hardware acceleration and emulation platforms
• Partition verification environments between the host and emulator while ensuring functional correctness and optimal performance
• Optimize verification environments to reduce compile time and improve execution efficiency
• Enable long-running regressions and software-driven validation on emulation platforms
• Integrate third-party Verification IP (VIP) and develop custom transactors as required
• Debug RTL, testbench, and emulation-related issues using waveform analysis and emulator debug tools
• Collaborate with RTL, Design Verification, Architecture, Firmware, and Software teams to accelerate project delivery.

Requirements

Required Skills

• Bachelor's in Electronics Engineering, Electrical Engineering, Computer Engineering, Computer Science, or a related fields
• 5+ years of experience in Design Verification, Hardware Emulation, or Simulation Acceleration for ASIC/SoC development
• Strong expertise in Cadence Palladium and/or Synopsys ZeBu
• Hands-on experience with SystemVerilog, UVM, and hardware emulation
• Experience porting verification environments to acceleration platform
• Strong understanding of RTL debugging, waveform analysis, and verification methodologies
• Experience with VIP integration and custom transactor development
• Knowledge of simulation acceleration, emulation flows, and regression automation
• Familiarity with scripting using Python, Perl, Tcl, or Shell

Preferred Qualification

• Experience with complex SoC/IP verification
• Knowledge of firmware-assisted verification and software-driven validation
• Familiarity with CI/CD and regression automation
• Strong debugging, analytical, and problem-solving skills
• Excellent communication and cross-functional collaboration skills

Key Responsibilities

• Maintain and optimize simulation acceleration and emulation environments using Cadence Palladium and/or Synopsys ZeBu
• Port SystemVerilog/UVM verification environments to hardware acceleration and emulation platforms
• Partition verification environments between the host and emulator while ensuring functional correctness and optimal performance
• Optimize verification environments to reduce compile time and improve execution efficiency
• Enable long-running regressions and software-driven validation on emulation platforms
• Integrate third-party Verification IP (VIP) and develop custom transactors as required
• Debug RTL, testbench, and emulation-related issues using waveform analysis and emulator debug tools
• Collaborate with RTL, Design Verification, Architecture, Firmware, and Software teams to accelerate project delivery.

Required Skills

• Bachelor's in Electronics Engineering, Electrical Engineering, Computer Engineering, Computer Science, or a related fields
• 5+ years of experience in Design Verification, Hardware Emulation, or Simulation Acceleration for ASIC/SoC development
• Strong expertise in Cadence Palladium and/or Synopsys ZeBu
• Hands-on experience with SystemVerilog, UVM, and hardware emulation
• Experience porting verification environments to acceleration platform
• Strong understanding of RTL debugging, waveform analysis, and verification methodologies
• Experience with VIP integration and custom transactor development
• Knowledge of simulation acceleration, emulation flows, and regression automation
• Familiarity with scripting using Python, Perl, Tcl, or Shell

Preferred Qualification

• Experience with complex SoC/IP verification
• Knowledge of firmware-assisted verification and software-driven validation
• Familiarity with CI/CD and regression automation
• Strong debugging, analytical, and problem-solving skills
• Excellent communication and cross-functional collaboration skills