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Senior Software Engineer
Jobot
New York, NY
- $150,000 to $200,000 USD / year
Senior Software Engineer | Building the Future of AI-Powered Identity & Digital Trust | Go, TypeScript, AI Agents | NYC / SF
Added just now
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Senior Software Engineer
Jobot
San Francisco, CA
- $150,000 to $200,000 USD / year
Senior Software Engineer | Building the Future of AI-Powered Identity & Digital Trust | Go, TypeScript, AI Agents | NYC / SF
Added 7 mins ago
Engineer Senior Principal II - Ground Systems
BAE Systems
Aurora, CO
We are looking to expand our team with a talented and energetic systems engineer in support of development of ground systems for commercial, DoW, and other government customers. This…
Added 7 mins ago
Tier 3 Ground Terminal (GT)/ IT Engineer- Junior, Intermediate and Senior Level- TS/SCI with Polygraph
General Dynamics Information Technology
Aurora, CO
Transform technology into opportunity as the Tier 3 Ground Terminal (GT) / IT Engineer provides support for the sustainment of satellite GT antenna, Radio Frequency (RF), communications,…
Added 7 mins ago
Staff Embedded Software Engineer
Stryker
San Jose, CA
We are looking for a Staff Embedded Software Engineer who enjoys combining hands-on software development with technical ownership.
Added 7 mins ago
Staff Embedded Software & Controls Engineer
Stryker
Flower Mound, TX
This is an opportunity for an engineer who likes to write code, run experiments, understand physical system behavior, work directly with hardware, and keep investigating until the root…
Added 11 mins ago
Systems Engineer and Modeler
Booz Allen Hamilton_United States
Huntsville, AL · Arnold AFB, TN
As a Systems Engineer on our team, you’ll have the chance to lead the technical development and integration of Department of Defense systems. You’ll create, integrate, and apply…
Added 16 mins ago
Applications Engineer (Mining Mobile Plant)
Bradken
Mesa, AZ
We are seeking an Applications Engineer to support the development, improvement, and customization of Bradken's mining equipment product lines, with a primary focus on Crawler Systems for…
Added 33 mins ago
O
RTL Design Engineer, Networking / NoC
OpenAI
San Francisco, CA
- $287,000 to $485,000 USD / year
We’re looking for an RTL Design Engineer to help design and develop next-generation AI accelerator silicon. In this role, you'll work across architecture, microarchitecture, and RTL…
Added 1 hour ago
Technical Lead, Systems Engineering & Validation - US Naval
Rolls-Royce
United States
…program management as well as acting as a delegate for the Chief Engineer. The role also provides governance on all Naval GTM system engineering…
Added 1 hour ago
Senior Test Engineer, Lunar
Vast
Long Beach, CA
Vast is looking for a Senior Test Engineer to support our Lunar Program, reporting to the Senior Vice President, Lunar Programs. As the first dedicated test hire on the program, you will be…
Added 1 hour ago
RF Systems Engineer
Vast
Long Beach, CA
As an RF Systems Engineer, you will manage communication system requirements and verification for space stations and satellites. Your responsibilities will include RF system design, link…
Added 1 hour ago
Senior Staff Radar Modeling Simulation & Analysis Systems Engineer
CORP-Corporate Office
United States
Northrop Grumman Mission System’s Engineering and Sciences (E&S) Baltimore and Partnered Sites (BaPs) Division is seeking a Senior Staff Radar Modeling Simulation & Analysis Systems…
Added 1 hour ago
Sr. Staff Optomechanical Engineer - 6
SP - Launch Vehicles
United States
Northrop Grumman Space Systems is looking for a Sr. Staff Optomechanical Engineer to support the Electro-Optics Group within the Launch Vehicles business unit in Chandler, Arizona.
Added 1 hour ago
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Lead Principal Core Infrastructure Engineer
Oracle
Nashville, TN
- $146,300 to $306,400 USD / year
…services. Establishes KPIs and advanced telemetry; applies formal verification for complex features; and develops robust replication/synchronization strategies. Advises and leads resolution…
Added 1 hour ago
O
Lead Principal Core Infrastructure Engineer
Oracle
Nashville, TN · Seattle, WA
- $146,300 to $306,400 USD / year
As a Lead Principal Core Infrastructure Engineer on Oracle's Strategic Customer Engineering team, you will play a critical role in driving complex technical initiatives across Oracle Cloud…
Added 1 hour ago
Senior Mechanical Design Engineer
Intuitive
Sunnyvale, CA
…invasive care, our technologies - like the da Vinci surgical system and Ion - have transformed how care is delivered for millions of patients…
Added 1 hour ago
Indigo Technical Field Service Product Specialist
HP
Remote, United States
…responsible for delivering advanced technical support, installations, system upgrades, performance optimization, customer training, and escalation management to ensure maximum press uptime,…
Added 1 hour ago
OC
Assistant Engineer (Commissioning)
Orange County Sanitation District
Fountain Valley, CA
- $122,283.2 to $148,574.4 USD / year
OC San is currently looking to fill the role of an Assistant Engineer (Commissioning).
Added 1 hour ago
Senior Mechanical Design Engineer (Core Components)
System One
Bellevue, WA
Job Title: Senior Mechanical Design Engineer (Core Components)
Added 1 hour ago
Principal/Senior Principal Space Systems Engineer Mission Architect*
Northrop Grumman
Chantilly
Developing and managing mission, system, and subsystem requirements, including decomposition, allocation, traceability, verification, and validation.
Added 1 hour ago
Principal Engineer Supplier Quality/Sr Principal Engineer Supplier Quality
Northrop Grumman
Baltimore
Northrop Grumman Mission Systems sector is seeking a Principal or Senior Principal Supplier Quality Engineer to join our Tactical Fighters team at the Baltimore location.
Added 1 hour ago
Systems Engineer or Principal Systems Engineer
Northrop Grumman
Ocean Springs
The integration and test efforts associated with naval electronic system design are critical to the deployment of capable vessels in the service of our Navy and Coast Guard. Northrop…
Added 1 hour ago
Sr. Principal Flight Avionics Responsible Engineer (Level 4)
Northrop Grumman
Melbourne
Northrop Grumman’s Aeronautics Systems sector is seeking a Sr. Principal Flight Avionics Responsible Engineer to join our team of qualified, diverse individuals in defining the future. This…
Added 1 hour ago
Principal/Senior Principal Space Systems Engineer Interface Management*
Northrop Grumman
Chantilly
As a Space Systems Engineer, you’ll help shape the spacecraft and mission across the full lifecycle - from mission architecture and concept development through detailed analysis,…

OpenAI

RTL Design Engineer, Networking / NoC

San Francisco, CA, United States

$287,000 to $485,000 USD / year

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Job details

Pay: $287,000 to $485,000 USD / year
Posting language: English
Posted: Nov 9, 2026

Original job description

About the Team

OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. The team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.

About the Role

We’re looking for an RTL Design Engineer to help design and develop next-generation AI accelerator silicon. In this role, you'll work across architecture, microarchitecture, and RTL implementation, translating complex system and performance requirements into efficient, scalable hardware designs.

You'll collaborate closely with silicon architects, hardware and software engineers, verification, and physical design teams to co-design hardware solutions optimized for demanding AI workloads. This is a hands-on engineering role with opportunities to influence architectural decisions, drive microarchitecture development, and own RTL design from early concept through implementation and integration.

We're particularly interested in engineers with experience in Network-on-Chip (NoC), networking, interconnect architectures, or high-performance data movement, though the role encompasses broader RTL design and hardware co-design challenges.

In this role, you will:

Design and implement high-performance RTL for next-generation AI accelerator silicon, from microarchitecture definition through implementation and integration.
Collaborate with architecture and software teams to translate system-level requirements into efficient hardware microarchitectures.
Drive hardware/software co-design efforts to optimize performance, power, area, and scalability for AI workloads.
Develop and optimize RTL for complex datapaths, control logic, interconnects, and other critical silicon subsystems.
Evaluate architectural and microarchitectural tradeoffs across bandwidth, latency, throughput, and resource utilization.
Partner with design verification and formal verification teams to ensure functional correctness, develop verification strategies, and debug complex design issues.
Work closely with physical design teams to optimize RTL for synthesis, timing closure, power, and area.
Contribute to architecture reviews, design specifications, and cross-functional discussions to influence future silicon designs.
Support block-level and SoC-level integration, debugging, and performance optimization.

You might thrive in this role if you:

Have strong hands-on experience with ASIC RTL design and microarchitecture development using SystemVerilog or Verilog.
Have experience designing and implementing complex digital hardware blocks, from architecture and specification through RTL development and verification.
Understand hardware architecture and microarchitecture tradeoffs, including performance, power, area, latency, and throughput.
Have experience collaborating across architecture, software, verification, and physical design teams to develop optimized hardware solutions.
Can reason about complex hardware systems, identify performance bottlenecks, and translate architectural requirements into efficient RTL implementations.
Have experience with synthesis, timing closure, and physical implementation considerations.
Enjoy working on ambiguous, technically challenging problems and taking ownership of designs from concept through integration.
Bring experience with Network-on-Chip (NoC), networking, interconnect fabrics, packet-based architectures, or high-bandwidth data movement systems.
Experience with AI accelerators, high-performance computing, or hardware/software co-design is a plus.

To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.

For additional information, please see OpenAI’s Affirmative Action and Equal Employment Opportunity Policy Statement https://cdn.openai.com/policies/eeo-policy-statement.pdf.

Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations.

To notify OpenAI that you believe this job posting is non-compliant, please submit a report through this form https://form.asana.com/?d=57018692298241&k=5MqR40fZd7jlxVUh5J-UeA. No response will be provided to inquiries unrelated to job posting compliance.

We are committed to providing reasonable accommodations to applicants with disabilities, and requests can be made via this link https://form.asana.com/?k=bQ7w9h3iexRlicUdWRiwvg&d=57018692298241.

OpenAI Global Applicant Privacy Policy https://cdn.openai.com/policies/global-employee-and-contractor-privacy-policy.pdf

At OpenAI, we believe artificial intelligence has the potential to help people solve immense global challenges, and we want the upside of AI to be widely shared. Join us in shaping the future of technology.

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Skills

RTL
Design hardware
Debugging
SystemVerilog
Verilog

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