Jobs in the United States

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Added 42 mins ago
Distinguished Hardware Engineer
Cisco
San Jose, CA
As a Distinguished Engineer, you will serve as a technical visionary and advisor to Cisco’s engineering business and senior management. You will lead and influence key industry boards,…
Added 1 day ago
Principal Engineer, Project Management - Chip Power
NVIDIA Corporation
North District, IL
NVIDIA Switches ASIC group is seeking a top-tier ASIC Power technical manager to lead the development of our next-generation ASICs Power execution, modelling, and optimization. Join us in…
Added 2 days ago
Senior CAD Engineer - Layout/Verification/Simulation
Micron Technology, Inc.
Boise, ID · San Jose, CA
Develop, enhance, and debug CAD tools, automation, and flows for custom IC design, layout, simulation, and verification.
Added 2 days ago
Senior CAD Engineer - Layout/Verification/Simulation
Micron Technology
Boise · San Jose
JR116732 Senior CAD Engineer - Layout/Verification/Simulation (Evergreen)
Added 2 days ago
Senior CAD Engineer – Physical Verification
Micron Technology
Boise · San Jose
JR116730 Senior CAD Engineer – Physical Verification (Evergreen)
Added 2 days ago
Senior CAD Engineer – Physical Verification
Micron Technology, Inc.
Boise, ID · San Jose, CA
Lead technical projects and contribute to the physical verification roadmap.
Added 3 days ago
Senior Design Verification Engineer
Micron Technology, Inc.
San Jose, CA
As a Senior Design Verification Engineer, you will develop and support the tools, automation, and flows used to design, verify, and tape out advanced memory products. You will work closely…
Added 3 days ago
Senior CAD Engineer – Physical Verification
Micron Technology, Inc.
Boise, ID
Lead technical projects and contribute to the physical verification roadmap.
Added 3 days ago
ASIC Design - Floorplan Engineer
Avago Technologies U.S. Inc.
United States
Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for…
Added 4 days ago
VLSI Physical Design Lead Engineer
Hewlett Packard Enterprise
Ft. Collins, CO · Chippewa Falls, WI · Bloomington, MN
Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Influences architecture and logic design and builds physical implementations through development of…
Added 4 days ago
VLSI Physical Design Engineer
Hewlett Packard Enterprise
Ft. Collins, CO · Chippewa Falls, WI · Bloomington, MN
Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for…
Added 4 days ago
IC
EDA Tools Software Engineer
Intel Corporation
OR
- $95,640 to $181,940 USD / year
…Technology Development), you will be responsible for process design rule definition, construction and validation of lead certification Tape-in Collaterals for Intel's next generation…
Added 4 days ago
IG
Senior ASIC Design Engineer
Insight Global
Vancouver, WA
- $116,000 to $180,000 USD / year
BS or MS in Electrical Engineering or equivalent, with VLSI design experience
Added 6 days ago
IC
Intel Foundry LTD Product Yield Development Engineer
Intel Corporation
OR · TX · AZ
- $220,920 to $311,890 USD / year
Degree in electrical engineering, computer science, VLSI design, physics
Added 6 days ago
IC
Senior Analog and Mixed Signal Design Engineer
Intel Corporation
OR · CA
- $141,910 to $269,100 USD / year
Lead transistor-level design of critical SerDes blocks: TX drivers (SST/CML) with FFE, RX AFE (CTLE, VGA, termination, T-coil and ESD co-design), DFE and slicers, time-interleaved ADC front…
Added 9 days ago
ASIC / FPGA Digital Design Engineer – (Associate or Experienced)
The Boeing Company
El Segundo, CA
Strong digital design fundamentals (coursework in digital logic design, computer architecture, ASIC design flow, VLSI Design, etc.)
Added 10 days ago
Staff VLSI Design Engineer
SanDisk
Milpitas, CA
…center of innovation. We are looking for an experienced Staff Engineer to lead and deliver projects for our Memory Design team. This is a great opportunity for a results-oriented,…
Added 10 days ago
Sr. Staff Engineer, System Design Engineering
SanDisk
Milpitas, CA
System Design for HBF-based products for mobile and datacenter applications.
Added 11 days ago
Memory Architect
Normal Computing Corporation
Mountain View, CA
…In-Memory Computing architecture and as Memory Architect you will lead the translation of these concepts from theory into silicon. You will have free rein to completely reimagine each…
Added 11 days ago
Product Yield Enhancement Development Failure Analysis Engineer (High Bandwidth Memory)
Micron Technology
Boise
…HBM (High Bandwidth Memory) Product Yield Enhancement PDFA Engineer position open where you will work on the Product Development Failure Analysis team to take next generation HBM devices…
Added 13 days ago
AM
Senior Microprocessor VLSI Physical Design Engineer
Advanced Micro Devices
Fort Collins, CO
- $178,400 to $267,600 USD / year
…client, and gaming business. We are looking for an experienced VLSI physical design engineer to join this innovative team as a technical expert. The candidate will be a key contributor and…
Added 13 days ago
Senior CAD Engineer – Physical Verification
Micron Technology
Boise
JR114916 Senior CAD Engineer – Physical Verification
Added 15 days ago
Senior Design Verification Engineer
Micron Technology
San Jose
As a Senior Design Verification Engineer, you will develop and support the tools, automation, and flows used to design, verify, and tape out advanced memory products. You will work closely…
Added 15 days ago
CAD and Integration Engineer, Silicon
Meta
Sunnyvale, CA
Meta is seeking a lead CAD and integration engineer to shape the methodology and physical implementation infrastructure for our custom silicon programs. Working at the intersection of…
Added 16 days ago
Principal Engineer-Design (SoC Integration and RTL/IP)
Microchip - USA
Chandler, AZ
The dsPIC microcontroller group is seeking an experienced SoC Integration, RTL/IP Design, and FPGA Engineer to lead SoC integration, RTL development, IP design, and FPGA prototyping…

Normal Computing Corporation

Memory Architect

Mountain View, CA, United States

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Job details

Posting language: English
Posted: Oct 22, 2026

Original job description

NORMAL COMPUTING | BUILD WITH US

Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), and London.

THE ROLE

Normal is building AI inference hardware based on our revolutionary new Thermo In-Memory Computing architecture and as Memory Architect you will lead the translation of these concepts from theory into silicon. You will have free rein to completely reimagine each element of a conventional memory; from the design and layout read/write paths, organization of memory arrays, to the development of a microarchitecture which seamlessly interleaves core memory operations with high performance compute. Ultimately, you will be responsible for delivering 100-1000× improvements in performance in AI inference.

You will report to the Director of Silicon Engineering and partner with scientists, microarchitects, physical design, and analog design engineers to implement a new standard cell library which combines existing digital compute primitives with Normal’s ThermoDRAM compute primitives. You will translate these new compute primitives into a highly performant Compute In-Memory System. You will own the technical relationship with major manufacturers from PDK acquisition through tapeout of test chips and production silicon.

This role requires a seasoned engineer with prior experience in memory technology but who understands that radical performance improvements require radical paradigm shifts.

WHAT YOU WILL OWN

Architecture for Processing-In-Memory: Define the memory requirements and floorplan that enable in-memory compute capability. This includes not only read/write paths to ALUs but also novel memory primitives. Specify the read/write circuitry row/column decoders that enable novel memory and in-memory compute operations.
Internal Bandwidth and Data Movement: Architect the local and global datapaths, segmented buses and on-die fabrics that move data between memory arrays and logic.
Power Grid and Reliability: Own power distribution, power budgets, thermal limits, redundancy, and ECC so that peak memory and compute performance can be extracted from the system without damaging retention or yield
PDK and Fab Path: Own access to process design kits and design rules and assess the limits and potential of architectural modifications which can be supported by existing design rules. Drive tapeout plan starting with an upcoming shuttle through test-chip content, schedule, and bring-up.
Primitive Device Library: Partner with our analog engineers who build and characterize the primitive device library (write circuits, drivers, multiplexers). Set requirements and ensure design choices drive architectural performance considerations.
Memory Interfaces: Define how our custom memory product interfaces to external hosts including SERDES, PCIE, Ethernet, DDR5, LP6, or HBM-class interfaces, command-set extensions, and controller/timing implications that impact performance.
Modeling and Validation: Oversee development of SPICE, analytical, and cycle-level models of performance, power, and yield. Partner with performance and machine learning engineers to ensure projected PPA improvements translate into workload level gains.

WHAT MAKES YOU A GREAT FIT

Substantial experience in memory architecture or circuit design at a memory manufacturer or a memory-centric compute company.
Deep understanding of memory array physics: 1T/3T/6T/8T SRAM cells, DRAM bitcells, capacitance, sensing, read/write operations, core timing, retention, and reliability
Hands-on experience with embedded memory or random access memory technology and PDKs with experience developing memory test chips through tapeout
Fluency moving between Spice-level circuit behavior through architecture-level performance and power models with strong fundamentals in one or more programming language (e.g. Python, C, C++) for modeling and performance prediction
Experience in RTL and SystemVerilog to model and optimize dataflow and specify compute block requirements
Experience with different interface types including memory interfaces
Excellent written and spoken communication skills

BONUS POINTS

Experience with process-in-memory or near-memory compute
Experience with non-volatile memory technology
Experience with DRAM technology including eDRAM
Major publications at ISSCC, VLSI, IEDM, ISCA or other major conferences
Existing relationships with manufacturers

Equal Employment Opportunity Statement

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.

Accessibility Accommodations

Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.

Privacy Notice

By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Applicant Privacy Notice https://normalcomputing.com/applicant-privacy-notice.

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Skills

Translation
Design process
Machine learning
Python
C
C++
RTL
SystemVerilog
Communication skills

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