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NAVITAS SEMICONDUCTOR USA, INC.

Principal Digital Design Engineer

Torrance, CA, United States

$170,000 to $190,000 USD / year

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Job details

Pay: $170,000 to $190,000 USD / year
Posting language: English
Posted: Oct 30, 2026

Original job description

Job Purpose:

Navitas Semiconductor (Nasdaq: NVTS) is a next-generation power semiconductor leader driving innovation in gallium nitride (GaN) and high-voltage silicon carbide (SiC) technologies. Our products enable faster, more efficient power delivery across AI data centers, high-performance computing, energy and grid infrastructure, and industrial electrification.

With more than 30 years of combined expertise in wide bandgap technologies, GaNFast™ power ICs integrate GaN power, drive, control, sensing, and protection, delivering faster power delivery, higher system density, and greater efficiency. GeneSiC™ high-voltage SiC devices leverage patented trench-assisted planar technology to provide industry-leading voltage capability, efficiency, and reliability for medium-voltage grid and infrastructure applications.

We are seeking a Principal Digital Design Engineer to join our fast-growing, collaborative team. The ideal candidate is self-motivated, energetic, and able to thrive in a high-growth, innovative environment, contributing directly to technologies that are shaping the future of power electronics.

Key Responsibilities and Duties:

• Design and implement digital blocks for ASICs using Verilog/SystemVerilog and standard ASIC design flows.

• Participate in pre-silicon simulation and verification using Cadence tools and standard cell libraries.

• Develop and maintain UVM/SystemVerilog testbenches, including functional coverage models, assertions (SVA), and constrained-random stimulus.

• Own coverage closure: analyze code and functional coverage, find gaps, and drive improvements in existing verification suites.

• Apply formal verification where it fits, such as property checking, connectivity, and register and FSM verification.

• Build mixed-signal verification using real-number modeling or AMS co-simulation to verify digital-analog interactions.

• Support ASIC tape-out activities, including synthesis, static timing analysis, and design signoff.

• After silicon returns from the foundry, focus on developing FPGA-based test builds (using Xilinx tools) to validate and characterize fabricated PMIC silicon.

• Interface and integrate digital control logic with analog/mixed-signal blocks commonly found in power management applications.

• Own digital architecture specs from product requirements through tape-out.

• Lead design and verification reviews, and follow coding, verification, and methodology standards set by the team.

• Mentor junior engineers and provide technical direction across multiple projects.

• Lead post-silicon debug and root-cause analysis, and feed silicon learnings back into design and verification.

• Evaluate and improve design and verification flows and tools to increase team productivity and reuse.

• Write and maintain automation scripts for regression testing, build flows, and hardware validation.

• Collaborate with cross-functional teams including analog designers, layout, validation, and test engineers to ensure robust and reliable PMIC design.

Knowledge, Skills, Abilities, and Other Characteristics (KSAO’s)

• Digital design principles: synchronous/asynchronous design, FSMs, clock-domain crossing, reset strategies, and low-power techniques.

• ASIC flow from start to finish: RTL, synthesis, STA, DFT, equivalence checking, place and route handoff, and signoff.

• Verification methodology: SVA, functional and code coverage, constrained-random testing, and formal verification concepts.

• PMIC and power electronics basics: DC-DC converter control, sequencing, protection and fault handling, trimming, and how digital logic interacts with analog blocks.

• Mixed-signal modeling and co-simulation concepts.

• Serial protocols: I²C, SPI, PMBus/SMBus.

• Standard cell libraries, timing constraints (SDC), and process corner/variation effects.

• Post-silicon validation and ATE test concepts.

• Hands-on with Cadence tools: Xcelium, Genus, Conformal, Modus, Tempus/Innovus, Voltus, etc.

• Xilinx Vivado and FPGA prototyping for silicon validation.

• Scripting and automation in Python, Tcl, Bash, Make, etc.

• Lab skills: oscilloscopes, logic analyzers, protocol analyzers, and bench equipment for silicon debug.

• Turning product-level requirements into digital architecture.

• Root-causing complex failures across pre-silicon, FPGA, and silicon environments.

• Balancing area, power, timing, schedule, and risk tradeoffs.

• Communicating technical issues across disciplines, including analog, layout, test, applications, and management.

• Managing several projects or blocks at once under tape-out deadlines.

• A mentoring mindset and commitment to raising team capability.

• Ability to exercise independence, ownership, and accountability over design contributions

• Drive to keep improving methodology, reuse, and automation.

• Attention to detail combined with a pragmatic, schedule-aware approach.

• Comfortable in a smaller team where larger impacts are required

Qualifications

Required Qualifications

Basic

• B.S. in Electrical Engineering, Computer Engineering, or a related field.

• 5+ years of industry experience in digital hardware design (ASIC, FPGA, or embedded hardware)

• Significant experience with SystemVerilog for design & verification

• Solid understanding of ASIC design flows including RTL design, synthesis, timing closure, and verification.

• Experience with digital simulation tools (e.g., Xcelium, Questa, Vivado Simulator).

• Experience with FPGA development using Xilinx tools (Vivado, ISE) for prototyping and silicon validation.

• Proficient in scripting (Python, TCL, Bash, etc.) for automation and test.

• Strong digital design fundamentals and hardware debugging skills.

• Proficient with versioning software (Git)

• Familiarity & experience in leveraging simulation and verification features

• Assertions, Linting, Threading

• Metric Driven Verification (Code, Conditional Branch, Toggle, FSM Branch, Functional, etc.)

Preferred

• M.S./PHD in Electrical Engineering, Computer Engineering, or a related field.

• 8+ years of industry experience in digital hardware design (ASIC, FPGA, or embedded hardware)

• Experience designing digital circuits for PMICs, DC-DC converters, battery management, or other power management products.

• Hands-on experience with standard cell logical synthesis including writing and refining SDC constraints.

• Experience with place and route including floor planning, placement, clock tree synthesis, routing, and timing closure.

• Experience with static timing analysis and signoff across corners and modes including timing ECOs.

• Experience with power integrity analysis

• Experience with logical equivalence checking across RTL, synthesized, and post-layout netlists.

• Familiarity with physical verification (DRC/LVS) and working with layout teams to resolve issues.

• Experience with DFT insertion and ATPG, and supporting ATE test bring-up.

• Experience with CDC analysis and lint signoff tools.

• Multiple successful tape-outs, ideally on mature mixed-signal or BCD processes common in power management.

• Familiarity with embedding third-party IP (MCUs, memories, etc.) within network of digital accelerators

What We Offer

• A front-row seat to the future of power electronics. Work on cutting-edge GaN and SiC technologies that are transforming AI data centers, electrification, and global energy infrastructure.

• A fast-paced, high-energy environment. We move quickly, make decisions with purpose, and empower employees to take ownership and drive real impact from day one.

• A team that shows up and delivers. We care deeply about our mission, our customers, and each other. We collaborate, support one another, and bring intensity and accountability to everything we do.

• Full support to succeed. You’ll have access to leadership, cross-functional collaboration, and the resources needed to innovate and execute at a high level.

• Competitive total rewards. Comprehensive health, dental, and vision coverage, unlimited PTO, and a competitive compensation package including base salary, bonus, and equity awards.

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More about this job

Skills

Power electronics
Verilog
SystemVerilog
AMS
Product comprehension
Root cause analysis
Design principles
RTL
DFT
Place-and-route
Python
Bash
Manage several projects
Coaching
Attention to detail
Electrical engineering
Computer engineering
Design hardware
Debugging
Git
ATPG

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