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Microsoft

Principal D2D SerDes & Analog Layout Design Engineer

CA, United States
Mountain View, CA, United States
Mountain View, United States

$142,800 to $304,200 USD / year

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Job details

Pay: $142,800 to $304,200 USD / year
Apply by: May 3, 2027
Posting language: English
Posted: Nov 4, 2026

Original job description

Overview

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s Intelligent Cloud mission. SCHIE delivers core infrastructure and foundational technologies supporting Azure, Microsoft 365, Teams, Xbox, and next-generation AI platforms at hyperscale, with a focus on high-quality, efficient, and trusted cloud hardware solutions. As Microsoft’s cloud and AI businesses continue to grow, high-speed die-to-die (D2D) connectivity is critical to delivering scalable, power-efficient custom silicon. The Semi & Custom IP team develops advanced analog and mixed-signal IP, including D2D SerDes interfaces, for next-generation AI accelerators, cloud infrastructure, and custom silicon platforms powering Microsoft’s future AI services and datacenter offerings. We are looking for a Principal D2D SerDes & Analog Layout Design Engineer to provide technical leadership for matching-critical analog layout and D2D SerDes physical implementation. This high-visibility role will establish layout strategy and methodology, lead complex subsystem execution across internal and external contributors, influence architecture and integration decisions, and drive production-ready IP from early feasibility through tapeout and silicon learning. The position offers broad organizational impact and opportunities to shape the long-term D2D and advanced-node layout capability for strategic silicon programs. #SCHIE

Responsibilities

Own the physical implementation strategy and technical execution for complex D2D SerDes and analog/mixed-signal subsystems in advanced process technologies, from early feasibility and architecture definition through tapeout, integration, and silicon learning.
Define top-level D2D analog front-end floorplans and integration strategies, including partitioning, hierarchy, die-edge constraints, bump or micro-bump alignment, ESD interfaces, power delivery, sensitive routing, clocking, and package-aware tradeoffs.
Establish matching, isolation, and parasitic-control methodology for critical circuits using symmetry, common-centroid placement, interdigitation, device-orientation control, dummy structures, shielding, guard rings, return-path planning, and gradient mitigation.
Lead technical execution across multiple blocks, engineers, and design partners by defining implementation plans, setting quality expectations, conducting design reviews, managing dependencies, and driving milestone and signoff closure.
Influence circuit, PHY, package, signal-integrity, physical-design, ESD, CAD, and SoC integration decisions by translating physical implementation limits and extracted-layout results into clear architectural recommendations.
Own resolution of the highest-impact layout risks for transmitter, receiver, clocking, bias, equalization, PLL/DLL, and related analog front-end circuitry, including ambiguous issues spanning block and organizational boundaries.
Drive physical verification and production-signoff strategy, including DRC, LVS, ERC, antenna, density, extraction review, EMIR, reliability analysis, layout-dependent effects, waiver judgment, and hierarchical closure.
Define and maintain layout quality criteria, review checklists, release requirements, signoff evidence, and technical acceptance criteria for internally and externally developed D2D and analog IP.
Guide delivery of production-ready IP collateral, including GDS/OASIS, LEF abstracts, integration views, interface documentation, waiver rationale, review records, and signoff packages for SoC and package integration.
Create and scale reusable analog-layout methodologies, templates, automation flows, and productivity solutions using SKILL, TCL, Python, Cadence APR, or similar technologies.
Provide technical direction and mentorship to senior engineers and partner teams, raise review quality, and grow organizational capability in advanced-node analog and D2D layout.
Govern technical execution with contractors, vendors, and geographically distributed design partners, including work partitioning, quality assessment, corrective action, and delivery accountability.
Communicate technical strategy, status, risks, options, and recommendations to engineering and program leadership, and drive alignment on decisions affecting multiple teams or silicon programs.
Identify longer-term technology, methodology, staffing, and enablement needs for future D2D and analog IP generations and translate them into actionable development plans.

Qualifications

Required Qualifications:

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.

Other:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Preferred Qualifications

8+ years of analog or mixed-signal layout experience, including matching-critical transistor-level layout and complex subsystem integration in advanced process technologies.
Experience leading analog, mixed-signal, SerDes, or D2D IP physical implementation through floorplanning, verification, signoff, tapeout, and integration.
Experience using Cadence Virtuoso and Siemens/Mentor Calibre physical verification tools.
Experience with DRC, LVS, ERC, antenna, extraction-aware layout, EMIR or reliability considerations, and advanced-node physical signoff.
Experience providing technical leadership across multiple layout contributors and influencing circuit design, CAD, package, signal-integrity, physical-design, or SoC integration teams.
Deep experience with high-speed SerDes, D2D interfaces, or comparable high-performance analog/mixed-signal IP, including transmitter, receiver, clocking, bias, equalization, PLL/DLL, or related circuitry.
Demonstrated expertise in analog matching, symmetry, layout-dependent effects, device orientation, process gradients, coupling, isolation, shielding, return paths, and parasitic optimization.
Experience with D2D standards or implementations such as UCIe, BoW, or proprietary die-to-die links.
Experience defining physical implementation strategy for advanced packaging and chiplet integration, including die-edge planning, bump or micro-bump interfaces, ESD, package escape, power delivery, and signal-integrity constraints.
Experience influencing circuit, interface, floorplan, or package decisions based on implementation feasibility, extraction, EMIR, reliability, and system-level tradeoffs.
Experience leading top-level assembly and verification of analog subsystems developed by multiple engineers, organizations, or external partners.
Experience with EMIR and reliability signoff using Ansys Totem, Cadence Voltus, or equivalent tools.
Experience with Cadence automated place-and-route (APR) flows, including floorplanning, placement, clock or signal routing, physical optimization, and integration of custom analog or mixed-signal IP with digitally implemented logic.
Strong automation and methodology-development skills using Python, SKILL, TCL, Perl, or similar languages.
Experience with FinFET and/or Gate-All-Around technologies and advanced nodes such as 5nm, 3nm, or beyond.
Demonstrated success mentoring senior engineers, establishing technical standards, resolving complex cross-organizational issues, and influencing engineering leadership.
Experience governing technical delivery across geographically distributed teams, contractors, vendors, or design-service partners over multiple milestones or programs.

This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

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