Req ID:
JR115925 SRAM Design Lead
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Overview:
Micron is seeking an experienced SRAM Design Engineer to develop high-performance, low-power embedded memory IP and testchip content. This is for advanced semiconductor technologies. The engineer will contribute across the complete memory-development lifecycle, including architecture definition, transistor-level circuit build, composing detailed circuit diagrams, layout interface, SPICE verification, timing and power characterization, compiler enablement, and pre- and post-silicon validation.
The role requires strong hands-on knowledge of SRAM and register-file design, memory arrays and bitcells, read/write datapaths, sense amplifiers, address decoding, control logic, assist techniques, and PPA tradeoffs. The candidate will work closely with teams handling layout development, CAD tools, manufacturing processes, testchip, product, silicon-test, and foundry. They will develop reliable, production-ready memory solutions and correlate models with measured silicon behavior.
Key Responsibilities
- Design and optimize custom SRAM, register-file, and embedded-memory circuits from architecture through schematic, layout support, characterization, and release.
- Develop and verify memory-array subsystems including bitcell arrays, precharge and equalization, sense amplifiers, write drivers, address decoders, wordline drivers, control logic, clocking, redundancy hooks, and read/write datapaths.
- Evaluate bitcell and peripheral-circuit stability, performance, leakage, dynamic power, and area across process, voltage, temperature, mismatch, and aging conditions.
- Own transistor-level simulation and signoff using HSPICE, Spectre, FineSim, or comparable tools, including PVT corners, Monte Carlo analysis, parasitic-aware post-layout simulatio and waveform/debug reviews.
- Drive SRAM PPA optimization through circuit sizing, architecture selection, banking and muxing decisions, assist techniques, bias strategies, retention modes, and critical-path analysis.
- Define timing, power, noise, and functional characterization methodologies and generate validated data for memory models, compiler views, SoC integration, and product signoff.
- Partner with layout engineers on floorplanning, bitcell-array composition, matching, critical-net routing, clock,also control distribution, parasitic reduction, and layout-dependent effects.
- Support memory-compiler development by defining legal configurations, architecture templates, circuit collateral, generation rules, validation checks, and release-quality views for multiple macro instances.
- Develop or improve automation for macro assembly, simulation setup, corner execution, results extraction, characterization, validation, and regression using Python, Tcl, Perl, SKILL, or similar languages.
- Plan and support SRAM testchips, including memory-instance selection, PPA objectives, test access, measurement structures, characterization plans. Alignment with process-learning goals.
- Lead pre-silicon verification, silicon bring-up, post-silicon characterization, failure debug, and model-to-silicon correlation in partnership with product and silicon-test teams.
- Create clear circuit specifications, design-review material, verification plans, characterization reports, and release documentation with traceable assumptions and decisions.
- Mentor engineers on memory-circuit fundamentals, simulation field, PPA analysis, debug methods, and reusable build practices.
- Explore AI-assisted engineering workflows for specification extraction, circuit and block partitioning, test-mode enrichment, design-flow automation, regression analysis and documentation while maintaining human technical review.
Technical Scope
- SRAM and register-file architectures, bit cell arrays, local and global datapaths, sensing, write paths, decoding, control, clocking, test access, and retention behavior.
- Low-power and high-performance design techniques including assist circuits, biasing, leakage reduction, dynamic-power optimization, robust low-voltage operation, and variation-aware sizing.
- Memory compilers and configurable macro generation. This includes architecture templating, legal configuration space, multi-view collateral, validation, and customer or SoC integration support.
- Circuit verification and characterization using SPICE, Verilog-based checks, PVT analysis, Monte Carlo mismatch, extracted post-layout simulation, and timing/power model correlation.
- Testchip development, silicon characterization, debug, shmoo analysis, margin assessment, model calibration and process collaboration.
Minimum Qualifications
- BS/MS/PhD in Electrical Engineering, Electronics, VLSI, Microelectronics, Computer Engineering, or a related field.
- Proven experience in SRAM, register-file, ROM, DRAM peripheral, or other custom-memory circuit design.
- Strong knowledge of CMOS transistor-level circuit design, memory architecture, static and dynamic timing behavior, power analysis, signal integrity, and process variation.
- Hands-on experience with Cadence Virtuoso and SPICE-class simulators such as HSPICE, Spectre, or FineSim.
- Experience performing PVT-corner, Monte Carlo, parasitic-aware post-layout, and power/timing characterization analyses.
- Ability to translate product or testchip requirements into circuit architecture, measurable design targets, verification plans, and release criteria.
- Experience collaborating with layout, CAD, process/foundry, verification, product, and chip testing groups.
- Clear technical communication and interpersonal skills.
- Ability to operate in a structured manner and problem solving ability.
- The ability to debug complex circuit or silicon issues using data and waveform evidence.
Preferred Qualifications
- Experience developing low-power SRAM compilers. Or register-file compilers across multiple technology nodes and foundries.
- Experience with bitcell stability analysis, assist schemes, retention modes, redundancy, test modes, compiler architecture, and generated-memory validation.
- Track record of taking memory IP from product definition and circuit design through layout, characterization, release, silicon correlation, and customer integration.
- Experience planning memory testchips and partnering with silicon test teams on characterization, debug, and correlation.
- Proficiency in Python, along with Tcl, Perl, SKILL, or related programming languages. Will be used for simulation, characterization, regression, and design-flow automation.
- Familiarity with RTL-to-GDS or digital-on-top methodologies for memory periphery and control logic, alongside full-custom array and critical-circuit design.
- Experience applying agentic AI, coding assistants, or custom LLM agents to specification processing, design automation, validation, or engineering productivity.
Job Profile(s):
Semiconductor Design Eng MTS
Relocation Level: TBD
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The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$153,000.00 - $267,000.00 a year
Additional compensation may include benefits, bonuses and equity. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
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