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Lead Software Engineer-Marketing Technology
AAPC
Remote, United States
AAPC seeks a hands-on lead software engineer to help build and evolve the customer-facing digital products, e-commerce experiences, and marketing technology that take people from discovery…
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AI/ML Automation Engineer/Developer (Jr, Mid and Sr.)
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Parsons is growing its team of AI/ML Automation Engineers/Developers (at several levels) to support upcoming mission-critical cybersecurity work. If you enjoy performing cutting-edge…
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Software Engineer (Full Stack Developer) - Remote
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We are seeking a highly motivated Software Engineer (Full Stack Developer) to design, develop, and support modern enterprise web applications. In this role, you will work across the full…
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Greenfield Manager, Startups
Vercel
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Lead Value Engineer - CGPR
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We are looking for a Lead Value Engineer, Consumer Packaged Goods (CPG) - an industry expert who can bridge the gap between technical process mining, AI-driven automation, and strategic…
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Senior Software Engineer - Lab Automation
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As a Senior Software Engineer – Lab Automation, you will be the essential bridge connecting software architecture, frontier AI models, and real-world physical instrumentation. You will…
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Senior AWS Database Migration Architect / Engineer
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Manufacturing Engineer
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- $82,000 to $112,000 USD / year
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Travel Control Systems Engineer
Actalent
Washington, DC
- $39 to $50 USD / hour
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Travel Control Systems Engineer
Actalent
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- $39 to $50 USD / hour
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Travel Control Systems Engineer
Actalent
Columbus, OH
- $39 to $50 USD / hour
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Travel Control Systems Engineer
Actalent
Atlanta, GA
- $39 to $50 USD / hour
Job Title: Controls Systems EngineerJob DescriptionThe Controls Systems Engineer role is a full-time, travel-based position that moves from project to project, with typical assignments…
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Controls Engineer
Actalent
Sturgis, MI
- $30 to $40 USD / hour
This Controls Engineer will focus on designing, programming, and commissioning control systems for custom automated machinery. Develop PLC software using ladder logic and structured text,…
Added 14 mins ago
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Process Engineer
Actalent
Noblesville, IN
- $48.08 to $52.88 USD / hour
Job Title: Process EngineerJob DescriptionThe Process Engineer provides engineering support for manufacturing equipment and processes used to produce plastic medical components. This role…
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Travel Control Systems Engineer
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Chicago, IL
- $39 to $50 USD / hour
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Process Improvement Engineer
Actalent
Champaign, IL
- $48.08 to $52.88 USD / hour
Job Title: Process Improvement EngineerJob DescriptionThis role focuses on enhancing engineering processes by applying artificial intelligence, automation, and data-driven solutions. The…
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Travel Control Systems Engineer
Actalent
Denver, CO
- $39 to $50 USD / hour
Job Title: Controls Systems EngineerJob DescriptionThe Controls Systems Engineer role is a full-time, travel-based position that moves from project to project, with typical assignments…
Added 14 mins ago
Mechanical Engineer
Actalent
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…on setting up start models and drawings that support design automation projects, ensuring they follow established modeling best practices. You will create and execute test specifications to…
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Travel Control Systems Engineer
Actalent
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Added 16 mins ago
Staff Software Engineer
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As the Staff Software Engineer, you'll be the senior technical anchor for MillerKnoll's Salesforce Commerce Cloud storefronts, including Herman Miller, Design Within Reach, and Knoll. We're…
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Early Career - Network Engineer (RAN Optimization)
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Junior Software Engineer- AI
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Principal Software Engineering
AT&T Services, Inc.
Remote, United States
- $174,100 to $261,100 USD / year
As a Principal Software Engineering, you will be a lead architect for AT&T's AI-powered tools, automation platforms, and Agentic AI ecosystem, responsible for building and scaling the…
Added 19 mins ago
Senior Engineer - Protection & Control
THE UNITED ILLUMINATING COMPANY
United States Of America, CT
Job Title: Senior Engineer – Protection & Control

Closed listing

SoC Physical Design Engineer

Austin, TX, United States

This opening has closed.

The original listing is kept below for reference.

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Job details

Experience: 8+ years of experience in SoC or ASIC physical design
Posting language: English
Posted: Nov 3, 2026

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Original job description

Archived listing. The details below describe a past opening.

Summary:

Meta’s mission is to give people the power to build community and bring the world closer together. Our global teams are constantly iterating, solving problems, and working together to empower people around the world to build community and connect in meaningful ways. Together, we can help people build stronger communities. We are just getting started.Reality Labs focuses on delivering Meta’s vision through creating advanced AI enabled wearables. The compute performance and power efficiency requirements of wearables require custom silicon. Reality Labs Silicon team is driving the state-of-the-art forward with breakthrough work in AI, augmented reality, computer vision, machine learning, graphics, displays, and sensors. Our chips will enable wearable devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms. As a Physical Design Engineer, you will collaborate closely with System-on-Chip (SoC) architects, front-end and back-end hardware designers, and power/performance teams to drive the physical implementation of IP, subsystems, and the chip top-level in advanced technology nodes. You will be responsible for developing custom methodologies across the physical design cycle – including floorplanning, physical synthesis, placement, clock-tree synthesis, routing, and static timing analysis – to optimize the power, performance, and area of the design while ensuring overall convergence. You will have the opportunity to bring cutting-edge technologies into a high-volume consumer product.

Required Skills:

SoC Physical Design Engineer Responsibilities:

Lead physical implementation, from floorplanning through tapeout, including physically-aware, ultra-low-power logic synthesis, place-and-route, static timing analysis, and EM/IR, at all levels of the SoC hierarchy
Define physical design methodology and flows to realize power and timing intent, and in doing so, meet milliwatt-level always-on power budgets in a wearable form factor, where thermal limits demand perf/mW compute efficiency
Identify and resolve physical implementation bottlenecks related to congestion, timing, and power
then develop automation and AI-assisted flows to improve throughput and QoR
Collaborate with RTL designers to provide implementation feedback that shapes the microarchitecture towards power- and area-efficient timing closure
Work closely with package engineers to ensure the floorplan, clock tree, and power plan meet the product-level power delivery, signal integrity, thermal, and routability requirements
Partner with design verification and DFx teams to ensure physical implementation supports gate-level functional correctness and meets debug and testability requirements
Drive EDA vendor engagement, tool evaluations, and flow improvements

Minimum Qualifications:

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
Bachelor’s degree in Electrical Engineering, Computer Engineering, relevant technical field, or equivalent practical experience
8+ years of experience in SoC or ASIC physical design
Hands-on RTL-to-GDSII experience in 3nm or below, including floorplanning, physical synthesis, placement, clock tree synthesis, routing, static timing analysis, and signoff
Experience with low-power implementation techniques, including power gating, voltage areas/islands, UPF, and DVFS
Experience with static timing analysis, including defining timing constraints, exceptions, and PVT corners/modes for functional and DFT signoff, and accounting for OCV/POCV and crosstalk effects
Experience working with EDA tools such as Fusion Compiler/Genus, ICC2/Innovus, PrimeTime/Tempus, RedHawk/Voltus, or equivalent
Proficiency in scripting (TCL, Python, or Perl) and reading Verilog netlists/RTL
Experience collaborating across RTL, DV, DFx, package, and vendor teams

Preferred Qualifications:

Ownership of block-level and/or full-chip power grid planning: dedicated macro supplies, power-switch chaining, MiM/decoupling caps, and EM/IR closure
Track record of defining signoff criteria and leading tapeout execution
Tapeout experience at 3nm or below
Experience adhering to and implementing responsible, ethical AI practices (e.g. risk assessment, bias mitigation, quality and accuracy reviews)
Experience applying ML-driven implementation (e.g. DSO.ai/Cerebrus) or LLM agents to flow debugging/QoR with measurable impact
Demonstrated ongoing AI skill development (e.g. prompt/context engineering, agent orchestration) and staying current with emerging AI technologies
Background in physically-aware synthesis of ultra-low-power designs, including custom recipes and app options, low-voltage PPA exploration, and UPF authoring
Management of the die area budget, including full-chip partitioning, beachfront allocations, channel planning, and pipeline/feedthrough insertion
Facility with advanced clock-tree synthesis, such as multi-source / H-tree, at block- and/or chip-level, including clock power reduction and hierarchical techniques
Experience leading chip-level timing closure across multi-corner/multi-mode scenarios, authoring I/O timing constraints, parsing flat timing reports, and implementing timing ECOs
Experience with 3D-IC structures (e.g., TSVs), EDA tools, and signoff methodologies
Master’s or PhD degree in Electrical Engineering, Computer Engineering, or equivalent area

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.

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Skills

Place-and-route
RTL
EDA
Computer science
Computer engineering
Electrical engineering
DFT
Python
Perl
Verilog
Hazard assessment
ML
Debugging

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