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Added 7 mins ago
CB
Process Engineer
Conagra Brands
Kent, WA
- $81,000 to $95,000 USD / year
…team capability. You will partner across functions to analyze performance, prioritize improvements, lead structured problem solving, and deliver small projects and capital initiatives that…
Added 7 mins ago
Software Development Engineer, Open Data Analytics Fundamentals Team
Amazon
Redmond, WA
…validate, register, and distribute AMIs and Docker images that power every cluster. We own the Kamino pipeline - the automated system that takes open-source frameworks and packages them…
Added 7 mins ago
A
Sr. Electrical Design Engineer IV
Actalent
Redmond, WA
- $70 to $81 USD / hour
We are seeking a Hardware Design Engineer to join a highly technical team focused on developing next-generation phased array antenna systems. This work supports customer terminal…
Added 7 mins ago
O
Senior Platform Software Engineer - OCI
Oracle
Olympia, WA
- $92,500 to $209,500 USD / year
Oracle Cloud Infrastructure (OCI) is looking for a Senior Platform Software Engineer to join the PKI team responsible for building and operating cloud-scale Public Key Infrastructure…
Added 7 mins ago
Senior Staff Engineer - Agentic Identity
Cisco
Olympia, WA
…innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with…
Added 7 mins ago
Senior Business Intelligence Engineer
Humana
Olympia, WA
The Senior Business Intelligence (BI) Engineer engages with business value streams on diverse and complex opportunities leveraging a variety of technology platforms. The individual will…
Added 7 mins ago
Supply Chain Capacity Engineer
Meta
Olympia, WA
Meta is seeking a Planning & Capacity Engineer to join the Infrastructure Supply Chain and Engineering (ISCE) Planning team to focus on planning optimization for all of Meta’s…
Added 7 mins ago
Frontend Engineer
GN Hearing
Olympia, WA
Help create seamless digital experiences that support people on their hearing journey. As a Frontend Engineer , you will build and evolve customer-facing web experiences for Jabra Enhance,…
Added 7 mins ago
Hardware Engineer, PCB Layout
Meta
Olympia, WA
Meta is seeking a Staff PCB Layout Engineer to drive the design and delivery of complex printed circuit boards for large-scale infrastructure hardware. In this role, you will define layout…
Added 7 mins ago
Software Development Engineer, Aurora Control Plane
Amazon
Seattle, WA
…database systems that provide availability, reliability and performance guarantees. This is a hands-on position where you will be asked to do everything from building rock-solid components…
Added 7 mins ago
Software Development Engineer, Amazon WorkSpaces
Amazon
Seattle, WA
…companies trust our robust suite of products and services to power their…
Added 7 mins ago
Senior Water Resources Manager, AWS Water Team
Amazon
Seattle, WA
…AWS data centers and all of the servers, storage, networking, power, and cooling equipment that ensure our customers have continual access to the innovation they rely on. We work on the…
Added 7 mins ago
Product Lifecycle Mechanical Engineer, Data Center Electrical Products and Services
Amazon
Seattle, WA
…AWS data centers and all of the servers, storage, networking, power, and cooling equipment that ensure our customers have continual access to the innovation they rely on. We work on the…
Added 7 mins ago
Software Development Engineer, Platform Engineering and Emerging Technologies
Amazon
Seattle, WA
The Platform Engineering and Emerging Technologies (PEET) team is hiring for a Software Development Engineer to support the development of AWS Secret Cloud for Industry! You'll design,…
Added 7 mins ago
Principal Software Engineer, Developer Platforms
Cisco
Seattle, WA
…innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with…
Added 7 mins ago
Software Development Engineer II, Core Selling Partner Experience
Amazon
Seattle, WA
…directly impacts millions of customers? As a Software Development Engineer II at Amazon, you will design, build, and deliver features that solve real problems and create meaningful value.…
Added 7 mins ago
Principal Product Manager-ES, Desktop Cloud Visualization (DCV)
Amazon
Seattle, WA
…workflows. It relies on Desktop Cloud Visualization (DCV), our high-performance display protocol, that provides Customers the ability to stream securely from any cloud/data center and…
Added 8 mins ago
Software Development Engineer II, EC2 Blackfoot Peering Team
Amazon
Seattle, WA
Amazon Elastic Compute Cloud (EC2) Networking is looking for a Software Development Engineer II to help build forwarding and encapsulation services that power large-scale networking within…
Added 8 mins ago
Field Service Engineer
Siemens
Seattle, WA
In this hands-on, field-based role, you’ll support customers by commissioning, testing, and troubleshooting power distribution and protection systems across a wide range of industrial…
Added 10 mins ago
RDK-B Firmware Developer
Infosys
United States
Experienced Engineer specializing in developing, integrating, testing, and maintaining broadband solutions on RDK-based devices such as gateways, and routers
Added 10 mins ago
RDKB Developer
Infosys
United States
Experienced Engineer specializing in developing, integrating, testing, and maintaining broadband solutions on RDK-based devices such as gateways, and routers
Added 12 mins ago
Commissioning Engineer, AWS Commissioning
Amazon Data Services, Inc.
Benton, LA
The Commissioning Engineer (CxE) provides testing and validation oversight of AWS data center electrical and mechanical infrastructure. CxEs review design documents, lead Factory Witness…
Added 12 mins ago
Commissioning Engineer, AWS Commissioning
Amazon Data Services, Inc.
New Carlisle, IN
The responsibilities of the ACx Commissioning Engineer (CxE) include, but are not limited to, oversight and coordination of multi-discipline division of work related to design review and…
Added 14 mins ago
Sr. Staff SoC BSW Core Engineer
Stellantis
Auburn Hills, MI
We are seeking a Sr. Staff SoC Platform SW Engineer with deep expertise in Android, QNX, Linux, and hypervisor-based systems to lead the development, integration, and optimization of…
Added 15 mins ago
Project Specialist II (Process Engineer) - ISO - CCM
Carlisle
Smithfield, Pennsylvania, PA
…globally, Carlisle offers stability, agility, and opportunity in a performance-driven culture. Do meaningful work and shape the future of building solutions; apply today and come grow with…

Closed listing

SoC Physical Design Engineer

Austin, TX, United States

This opening has closed.

The original listing is kept below for reference.

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Job details

Experience: 8+ years of experience in SoC or ASIC physical design
Posting language: English
Posted: Nov 3, 2026

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Original job description

Archived listing. The details below describe a past opening.

Summary:

Meta’s mission is to give people the power to build community and bring the world closer together. Our global teams are constantly iterating, solving problems, and working together to empower people around the world to build community and connect in meaningful ways. Together, we can help people build stronger communities. We are just getting started.Reality Labs focuses on delivering Meta’s vision through creating advanced AI enabled wearables. The compute performance and power efficiency requirements of wearables require custom silicon. Reality Labs Silicon team is driving the state-of-the-art forward with breakthrough work in AI, augmented reality, computer vision, machine learning, graphics, displays, and sensors. Our chips will enable wearable devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms. As a Physical Design Engineer, you will collaborate closely with System-on-Chip (SoC) architects, front-end and back-end hardware designers, and power/performance teams to drive the physical implementation of IP, subsystems, and the chip top-level in advanced technology nodes. You will be responsible for developing custom methodologies across the physical design cycle – including floorplanning, physical synthesis, placement, clock-tree synthesis, routing, and static timing analysis – to optimize the power, performance, and area of the design while ensuring overall convergence. You will have the opportunity to bring cutting-edge technologies into a high-volume consumer product.

Required Skills:

SoC Physical Design Engineer Responsibilities:

Lead physical implementation, from floorplanning through tapeout, including physically-aware, ultra-low-power logic synthesis, place-and-route, static timing analysis, and EM/IR, at all levels of the SoC hierarchy
Define physical design methodology and flows to realize power and timing intent, and in doing so, meet milliwatt-level always-on power budgets in a wearable form factor, where thermal limits demand perf/mW compute efficiency
Identify and resolve physical implementation bottlenecks related to congestion, timing, and power
then develop automation and AI-assisted flows to improve throughput and QoR
Collaborate with RTL designers to provide implementation feedback that shapes the microarchitecture towards power- and area-efficient timing closure
Work closely with package engineers to ensure the floorplan, clock tree, and power plan meet the product-level power delivery, signal integrity, thermal, and routability requirements
Partner with design verification and DFx teams to ensure physical implementation supports gate-level functional correctness and meets debug and testability requirements
Drive EDA vendor engagement, tool evaluations, and flow improvements

Minimum Qualifications:

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
Bachelor’s degree in Electrical Engineering, Computer Engineering, relevant technical field, or equivalent practical experience
8+ years of experience in SoC or ASIC physical design
Hands-on RTL-to-GDSII experience in 3nm or below, including floorplanning, physical synthesis, placement, clock tree synthesis, routing, static timing analysis, and signoff
Experience with low-power implementation techniques, including power gating, voltage areas/islands, UPF, and DVFS
Experience with static timing analysis, including defining timing constraints, exceptions, and PVT corners/modes for functional and DFT signoff, and accounting for OCV/POCV and crosstalk effects
Experience working with EDA tools such as Fusion Compiler/Genus, ICC2/Innovus, PrimeTime/Tempus, RedHawk/Voltus, or equivalent
Proficiency in scripting (TCL, Python, or Perl) and reading Verilog netlists/RTL
Experience collaborating across RTL, DV, DFx, package, and vendor teams

Preferred Qualifications:

Ownership of block-level and/or full-chip power grid planning: dedicated macro supplies, power-switch chaining, MiM/decoupling caps, and EM/IR closure
Track record of defining signoff criteria and leading tapeout execution
Tapeout experience at 3nm or below
Experience adhering to and implementing responsible, ethical AI practices (e.g. risk assessment, bias mitigation, quality and accuracy reviews)
Experience applying ML-driven implementation (e.g. DSO.ai/Cerebrus) or LLM agents to flow debugging/QoR with measurable impact
Demonstrated ongoing AI skill development (e.g. prompt/context engineering, agent orchestration) and staying current with emerging AI technologies
Background in physically-aware synthesis of ultra-low-power designs, including custom recipes and app options, low-voltage PPA exploration, and UPF authoring
Management of the die area budget, including full-chip partitioning, beachfront allocations, channel planning, and pipeline/feedthrough insertion
Facility with advanced clock-tree synthesis, such as multi-source / H-tree, at block- and/or chip-level, including clock power reduction and hierarchical techniques
Experience leading chip-level timing closure across multi-corner/multi-mode scenarios, authoring I/O timing constraints, parsing flat timing reports, and implementing timing ECOs
Experience with 3D-IC structures (e.g., TSVs), EDA tools, and signoff methodologies
Master’s or PhD degree in Electrical Engineering, Computer Engineering, or equivalent area

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.

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Skills

Place-and-route
RTL
EDA
Computer science
Computer engineering
Electrical engineering
DFT
Python
Perl
Verilog
Hazard assessment
ML
Debugging

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