Jobs in the United States

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Added 7 mins ago
Software Engineer, Systems ML
Meta
Pierre, SD
Meta is seeking a Software Engineer to join our Systems ML Engineering team, focused on building and optimizing the machine learning infrastructure that powers Meta's products at massive…
Added 18 mins ago
Software Engineer, Systems ML
Meta
Cheyenne, WY
Meta is seeking a Software Engineer to join our Systems ML Engineering team, focused on building and optimizing the machine learning infrastructure that powers Meta's products at massive…
Added 19 mins ago
CO
Environmental Engineer Manager
Commonwealth of Pennsylvania
Pittsburgh, PA
- $88,020 to $119,844 USD / year
Lead work that protects Pennsylvania’s land and water for future generations! As an Environmental Engineer Manager with the Department of Environmental Protection, you guide important…
Added 19 mins ago
CO
Environmental Engineering Specialist
Commonwealth of Pennsylvania
Norristown, PA
- $73,859 to $92,010 USD / year
One year of professional experience in environmental engineering and possession of an active Professional Engineer license issued by the Pennsylvania State Registration Board for…
Added 19 mins ago
CO
Senior Civil Engineer Supervisor (Transportation)
Commonwealth of Pennsylvania
Hollidaysburg, PA
- $80,646 to $104,959 USD / year
…that shape how communities move every day? As a Senior Civil Engineer Supervisor (Transportation) with the Pennsylvania Department of Transportation (PennDOT), you will guide projects from…
Added 29 mins ago
O
Civil Engineer II - City
OKC
Oklahoma City, OK
- $39.52 to $60.39 USD / hour
This position may be underfilled as a Civil Engineer I with a pay range of 516 - $35.81 - $54.80 hourly, or as an Engineer Intern with a pay range of 514 - $32.49 - $49.66.
Added 35 mins ago
Geotech and Pavement Bureau Chief
State of Montana
Helena, MT
Added 48 mins ago
Engineering Development Program, Test Equipment Design, Engineer I (Onsite)
RTX
United States
Pratt & Whitney Engineering Development Program Test Systems Engineering (TSE) is currently seeking Mechanical, Aerospace, and Systems Engineering students to support the test groups at…
Added 1 hour ago
J
Electrical Engineer (Control Systems)
Jobgether
Remote, United States
- $100,000 to $120,000 CAD / year
The ideal candidate is an experienced electrical or automation engineer with strong SCADA development and systems integration capabilities. They should combine practical technical expertise…
Added 1 hour ago
Senior Automated Test Engineer
Leidos
Tucson, AZ
Leidos is seeking a Senior Test Automation Engineer to help deliver mission-essential software capabilities that enable intelligence professionals to access critical information, analyze…
Added 1 hour ago
SCADA Engineer I
Panasonic
Sparks, NV
Do you want to join a team that's changing the world? Do you have a strong background as a SCADA Engineer I? Then we're looking for you! Check out the job description and apply now! Put…
Added 1 hour ago
Manufacturing Engineer I
Panasonic
Sparks, NV
Do you want to join a team that's changing the world? Do you have a strong background as a Manufacturing Engineer I? Then we're looking for you! Check out the job description and apply now!…
Added 2 hours ago
(Sr.) Engineer I (II)
PJM Interconnection, L.L.C.
Audubon, PA
Monitor and analyze existing project management methods and promote the development of new methods and the introduction of improved and emerging progress monitoring technologies in the…
Added 2 hours ago
Sr. Engineer I (II)
PJM Interconnection, L.L.C.
Audubon, PA
Join our dynamic team as a Engineer, where you'll play a critical role in advancing interconnection projects within the PJM New Service Request Cycle study process. This position is your…
Added 2 hours ago
Software Engineer I
Frontgrade
Colorado Springs, CO
The Software Engineer I participates in new and existing software developments. The role involves collaborating cross functionally to elicit requirements, design, build, test, deploy, and…
Added 2 hours ago
Senior Fullstack Engineer (Matchmaking)
Jobgether
Remote, United States
…and next steps. Our partner is looking for a Senior Fullstack Engineer (Matchmaking) based in the United…
Added 2 hours ago
R&D Engineer I
ITW
Mechanic Falls, ME
The R&D Laboratory Engineer I is responsible for conducting laboratory testing and supporting research and development efforts through data collection, analysis, documentation, and…
Added 2 hours ago
Spirit Defense - Mid-Level Research and Development Engineer
Spirit AeroSystems
Wichita, KS
Develop manufacturing processes and advanced technologies for aerostructure development and assembly
Added 2 hours ago
II
Systems Engineer I
Invictus International Consulting, LLC
Alexandria, VA
- Up to $150,000 USD / year
Analyze user requirements, CONOPS, and system architectures to develop requirements and support system design, development, integration, and implementation across the lifecycle
Added 2 hours ago
Engineer II-Sensor Test & Evaluation
Earthscope Consortium, Inc.
Socorro, NM
Job Title: Engineer II – Sensor Test and Evaluation
Added 2 hours ago
Roadway Engineer
WSP USA
Omaha, NE
WSP is currently initiating a search for a Civil/Roadway Engineer for our Omaha, NE office. Be involved in projects with our Nebraska Transportation Team and be a part of a growing…
Added 2 hours ago
W
Staff Engineer
Wonderly
Remote, United States
- $337,500 USD / year
Added 2 hours ago
DISTINGUISHED SCIENTIST/ENGINEER FOR USW THEATER OPERATIONS
Naval Sea Systems Command
Naval Base Newport, RI
Added 2 hours ago
Mechanical Engineer I -E&U
Affiliated Engineers, Inc
Chapel Hill, NC
…Design+Construction, Engineering News-Record, and Consulting-Specifying Engineer, with distinctions such as being named the #1 Laboratory Engineering Firm in the nation and receiving…
Added 3 hours ago
Lead Engineer I, Tech Product Manager 139528
KPMG LLP
Jackson, MS

Closed listing

SoC Physical Design Engineer

Austin, TX, United States

This opening has closed.

The original listing is kept below for reference.

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Job details

Experience: 8+ years of experience in SoC or ASIC physical design
Posting language: English
Posted: Nov 3, 2026

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Original job description

Archived listing. The details below describe a past opening.

Summary:

Meta’s mission is to give people the power to build community and bring the world closer together. Our global teams are constantly iterating, solving problems, and working together to empower people around the world to build community and connect in meaningful ways. Together, we can help people build stronger communities. We are just getting started.Reality Labs focuses on delivering Meta’s vision through creating advanced AI enabled wearables. The compute performance and power efficiency requirements of wearables require custom silicon. Reality Labs Silicon team is driving the state-of-the-art forward with breakthrough work in AI, augmented reality, computer vision, machine learning, graphics, displays, and sensors. Our chips will enable wearable devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms. As a Physical Design Engineer, you will collaborate closely with System-on-Chip (SoC) architects, front-end and back-end hardware designers, and power/performance teams to drive the physical implementation of IP, subsystems, and the chip top-level in advanced technology nodes. You will be responsible for developing custom methodologies across the physical design cycle – including floorplanning, physical synthesis, placement, clock-tree synthesis, routing, and static timing analysis – to optimize the power, performance, and area of the design while ensuring overall convergence. You will have the opportunity to bring cutting-edge technologies into a high-volume consumer product.

Required Skills:

SoC Physical Design Engineer Responsibilities:

Lead physical implementation, from floorplanning through tapeout, including physically-aware, ultra-low-power logic synthesis, place-and-route, static timing analysis, and EM/IR, at all levels of the SoC hierarchy
Define physical design methodology and flows to realize power and timing intent, and in doing so, meet milliwatt-level always-on power budgets in a wearable form factor, where thermal limits demand perf/mW compute efficiency
Identify and resolve physical implementation bottlenecks related to congestion, timing, and power
then develop automation and AI-assisted flows to improve throughput and QoR
Collaborate with RTL designers to provide implementation feedback that shapes the microarchitecture towards power- and area-efficient timing closure
Work closely with package engineers to ensure the floorplan, clock tree, and power plan meet the product-level power delivery, signal integrity, thermal, and routability requirements
Partner with design verification and DFx teams to ensure physical implementation supports gate-level functional correctness and meets debug and testability requirements
Drive EDA vendor engagement, tool evaluations, and flow improvements

Minimum Qualifications:

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
Bachelor’s degree in Electrical Engineering, Computer Engineering, relevant technical field, or equivalent practical experience
8+ years of experience in SoC or ASIC physical design
Hands-on RTL-to-GDSII experience in 3nm or below, including floorplanning, physical synthesis, placement, clock tree synthesis, routing, static timing analysis, and signoff
Experience with low-power implementation techniques, including power gating, voltage areas/islands, UPF, and DVFS
Experience with static timing analysis, including defining timing constraints, exceptions, and PVT corners/modes for functional and DFT signoff, and accounting for OCV/POCV and crosstalk effects
Experience working with EDA tools such as Fusion Compiler/Genus, ICC2/Innovus, PrimeTime/Tempus, RedHawk/Voltus, or equivalent
Proficiency in scripting (TCL, Python, or Perl) and reading Verilog netlists/RTL
Experience collaborating across RTL, DV, DFx, package, and vendor teams

Preferred Qualifications:

Ownership of block-level and/or full-chip power grid planning: dedicated macro supplies, power-switch chaining, MiM/decoupling caps, and EM/IR closure
Track record of defining signoff criteria and leading tapeout execution
Tapeout experience at 3nm or below
Experience adhering to and implementing responsible, ethical AI practices (e.g. risk assessment, bias mitigation, quality and accuracy reviews)
Experience applying ML-driven implementation (e.g. DSO.ai/Cerebrus) or LLM agents to flow debugging/QoR with measurable impact
Demonstrated ongoing AI skill development (e.g. prompt/context engineering, agent orchestration) and staying current with emerging AI technologies
Background in physically-aware synthesis of ultra-low-power designs, including custom recipes and app options, low-voltage PPA exploration, and UPF authoring
Management of the die area budget, including full-chip partitioning, beachfront allocations, channel planning, and pipeline/feedthrough insertion
Facility with advanced clock-tree synthesis, such as multi-source / H-tree, at block- and/or chip-level, including clock power reduction and hierarchical techniques
Experience leading chip-level timing closure across multi-corner/multi-mode scenarios, authoring I/O timing constraints, parsing flat timing reports, and implementing timing ECOs
Experience with 3D-IC structures (e.g., TSVs), EDA tools, and signoff methodologies
Master’s or PhD degree in Electrical Engineering, Computer Engineering, or equivalent area

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.

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More about this job

Skills

Place-and-route
RTL
EDA
Computer science
Computer engineering
Electrical engineering
DFT
Python
Perl
Verilog
Hazard assessment
ML
Debugging

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