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Added 1 min ago
Remote Substation Designer
Actalent
New Albany, OH
Develop a substation design layout with scoping information and general guidance from a Design Engineer.
Added 1 min ago
Electrical Design Engineer
Actalent
Austin, TX
Job Title: Electrical Design Engineer Location: Austin, TXJob DescriptionThe Electrical Design Engineer supports the planning and design of electrical infrastructure for commercial,…
Added 1 min ago
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Software Developer (Ignition/MES)
Actalent
Carrollton, TX
- $60 to $87 USD / hour
I'm currently hiring for a Software Engineer that has development experience in Ignition
Added 2 mins ago
ND
Data Centre Field Support Engineer (L2)
NTT DATA
TX
- $20 to $30 USD / hour
The Data Center Service Delivery Field Support Engineer (L2) is a developing engineering role, responsible for providing a professional second-line onsite technical support and field…
Added 2 mins ago
ND
Data Centre Field Support Engineer (L1)
NTT DATA
TX
- $19 to $24 USD / hour
The Data Center Service Delivery Field Support Engineer (L1) is an entry level engineering role, responsible for providing a professional first-line onsite technical support and field…
Added 2 mins ago
T
M365 Risk Engineer
TEKsystems
Irving, TX
- $50 to $65 USD / hour
Bachelors degree in computer science, information systems, cybersecurity, engineering, or equivalent practical experience.
Added 2 mins ago
ND
Cloud & Platform Engineer
NTT Data Americas, Inc.
Irving, TX
- $55 to $70 USD / hour
NTT DATA's Client is currently seeking a Cloud & Platform Engineer to join their team in Irving, Texas (US-TX), United States (US).
Added 2 mins ago
Sales Engineer, VisionLink Full Fleet Solutions
Caterpillar, Inc.
Irving, TX
The Sales Engineer, VisionLink Full Fleet Solutions serves as the technical lead within strategic sales opportunities, partnering with direct and dealer sales teams to position VisionLink…
Added 2 mins ago
Senior Robotics Engineer
Caterpillar, Inc.
Irving, TX
Programming: Knowledge of relevant programming languages and tools; ability to test, write, design, debug, troubleshoot and maintain source codes and computer programs.
Added 2 mins ago
Senior Principal Engineer
Autodesk
CA · San Francisco, CA · ON, CA · San Francisco
GET Engineering is seeking an experienced Senior Principal Engineer – AI and Engineering Excellence to lead the technical strategy and evolution of our cloud platform, developer experience,…
Added 2 mins ago
Sr. Manager, AI Engineer (Gen AI Platform Services: Agentic AI, Guardrails, Evaluation)
Capital One
NY · San Francisco, CA · McLean, VA · Cambridge, MA · San Jose, CA
The Intelligent Foundations and Experiences (IFX) team is at the center of bringing our vision for AI at Capital One to life. We work hand-in-hand with our partners across the company to…
Added 2 mins ago
Vascular Clinical Specialist (San Antonio)
Medtronic
San Antonio, TX
…independently mobile. The employee is also required to interact with a computer, and communicate with peers and co-workers. Contact your manager or local HR to understand the Work…
Added 2 mins ago
Sales Rep, Peripheral Nervous System (PNS) – San Antonio, TX
Medtronic
San Antonio, TX
Utilize computer-based customer/account management systems to track contacts, activity and follow up
Added 2 mins ago
Configuration Engineer (Hybrid) - 30857
Huntington Ingalls Industries
San Antonio, TX
…currently seeking a talented and experienced Configuration Engineer to join our team. As a Configuration Engineer, you will be responsible for defining, managing, and automating the build…
Added 2 mins ago
Lead Databricks Application Architect/Full Stack Developer
CGI Technologies and Solutions, Inc.
Dallas, TX
. Bachelor's degree in Computer Science, Engineering, Information Systems, or related field.
Added 3 mins ago
AVP Senior AI ML Engineer
Bank OZK
Dallas, TX
Bachelor’s degree in Computer Science, AI/ML, Data Science, or a related field, or commensurate work experience required.
Added 3 mins ago
GNC Engineer III
Capgemini
Houston, TX
Bachelor's degree in Mechanical Engineering, Electrical Engineering, Robotics, Automation Engineering, Computer Science, Information Technology, or a related engineering discipline.
Added 3 mins ago
Sr. Sales Representative, CAS
Medtronic
Houston, TX
…independently mobile. The employee is also required to interact with a computer, and communicate with peers and co-workers. Contact your manager or local HR to understand the Work…
Added 4 mins ago
Sr. Security Engineer, Field Innovation, Security Search and Observability (SSO)
Amazon
Austin, TX
We are hiring a Senior Security Engineer to work at the intersection of customer impact and AI. Our team builds and operates the detection, correlation, and vulnerability-management…
Added 4 mins ago
Dev Ops Engineer
Charles Schwab
Austin, TX
As a DevOps Engineer on the Enterprise Delivery Pipeline Engineering team, you will help build and operate secure, reliable platforms that enable developers to deliver software efficiently.…
Added 4 mins ago
SoC Physical Design Engineer
Meta
Austin, TX
…just getting started.Reality Labs focuses on delivering Meta’s vision through creating advanced AI enabled wearables. The compute performance and power efficiency requirements of wearables…
Added 4 mins ago
Senior Cybersecurity Architect (Cloud)
Amentum
Austin, TX
Engineer and administer cloud security posture management and workload protection capabilities, including environment onboarding, policy configuration, security recommendations, coverage,…
Added 4 mins ago
Cybersecurity Engineer (Cloud)
Amentum
Austin, TX
Added 4 mins ago
Executive Area Innovation Manager - GI Genius Sales - Endoscopy (Texas)
Medtronic
Austin, TX · Fort Worth, TX · Dallas, TX
Added 5 mins ago
Sr. Marketing Data & GTM Engineer
Konica Minolta Business Solutions, U.S.A., Inc.
Ramsey, NJ

Closed listing

SoC Physical Design Engineer

Sunnyvale, CA, United States

This opening has closed.

The original listing is kept below for reference.

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Job details

Experience: 8+ years of experience in SoC or ASIC physical design
Posting language: English
Posted: Nov 3, 2026

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Original job description

Archived listing. The details below describe a past opening.

Summary:

Meta’s mission is to give people the power to build community and bring the world closer together. Our global teams are constantly iterating, solving problems, and working together to empower people around the world to build community and connect in meaningful ways. Together, we can help people build stronger communities. We are just getting started.Reality Labs focuses on delivering Meta’s vision through creating advanced AI enabled wearables. The compute performance and power efficiency requirements of wearables require custom silicon. Reality Labs Silicon team is driving the state-of-the-art forward with breakthrough work in AI, augmented reality, computer vision, machine learning, graphics, displays, and sensors. Our chips will enable wearable devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms. As a Physical Design Engineer, you will collaborate closely with System-on-Chip (SoC) architects, front-end and back-end hardware designers, and power/performance teams to drive the physical implementation of IP, subsystems, and the chip top-level in advanced technology nodes. You will be responsible for developing custom methodologies across the physical design cycle – including floorplanning, physical synthesis, placement, clock-tree synthesis, routing, and static timing analysis – to optimize the power, performance, and area of the design while ensuring overall convergence. You will have the opportunity to bring cutting-edge technologies into a high-volume consumer product.

Required Skills:

SoC Physical Design Engineer Responsibilities:

Lead physical implementation, from floorplanning through tapeout, including physically-aware, ultra-low-power logic synthesis, place-and-route, static timing analysis, and EM/IR, at all levels of the SoC hierarchy
Define physical design methodology and flows to realize power and timing intent, and in doing so, meet milliwatt-level always-on power budgets in a wearable form factor, where thermal limits demand perf/mW compute efficiency
Identify and resolve physical implementation bottlenecks related to congestion, timing, and power
then develop automation and AI-assisted flows to improve throughput and QoR
Collaborate with RTL designers to provide implementation feedback that shapes the microarchitecture towards power- and area-efficient timing closure
Work closely with package engineers to ensure the floorplan, clock tree, and power plan meet the product-level power delivery, signal integrity, thermal, and routability requirements
Partner with design verification and DFx teams to ensure physical implementation supports gate-level functional correctness and meets debug and testability requirements
Drive EDA vendor engagement, tool evaluations, and flow improvements

Minimum Qualifications:

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
Bachelor’s degree in Electrical Engineering, Computer Engineering, relevant technical field, or equivalent practical experience
8+ years of experience in SoC or ASIC physical design
Hands-on RTL-to-GDSII experience in 3nm or below, including floorplanning, physical synthesis, placement, clock tree synthesis, routing, static timing analysis, and signoff
Experience with low-power implementation techniques, including power gating, voltage areas/islands, UPF, and DVFS
Experience with static timing analysis, including defining timing constraints, exceptions, and PVT corners/modes for functional and DFT signoff, and accounting for OCV/POCV and crosstalk effects
Experience working with EDA tools such as Fusion Compiler/Genus, ICC2/Innovus, PrimeTime/Tempus, RedHawk/Voltus, or equivalent
Proficiency in scripting (TCL, Python, or Perl) and reading Verilog netlists/RTL
Experience collaborating across RTL, DV, DFx, package, and vendor teams

Preferred Qualifications:

Ownership of block-level and/or full-chip power grid planning: dedicated macro supplies, power-switch chaining, MiM/decoupling caps, and EM/IR closure
Track record of defining signoff criteria and leading tapeout execution
Tapeout experience at 3nm or below
Experience adhering to and implementing responsible, ethical AI practices (e.g. risk assessment, bias mitigation, quality and accuracy reviews)
Experience applying ML-driven implementation (e.g. DSO.ai/Cerebrus) or LLM agents to flow debugging/QoR with measurable impact
Demonstrated ongoing AI skill development (e.g. prompt/context engineering, agent orchestration) and staying current with emerging AI technologies
Background in physically-aware synthesis of ultra-low-power designs, including custom recipes and app options, low-voltage PPA exploration, and UPF authoring
Management of the die area budget, including full-chip partitioning, beachfront allocations, channel planning, and pipeline/feedthrough insertion
Facility with advanced clock-tree synthesis, such as multi-source / H-tree, at block- and/or chip-level, including clock power reduction and hierarchical techniques
Experience leading chip-level timing closure across multi-corner/multi-mode scenarios, authoring I/O timing constraints, parsing flat timing reports, and implementing timing ECOs
Experience with 3D-IC structures (e.g., TSVs), EDA tools, and signoff methodologies
Master’s or PhD degree in Electrical Engineering, Computer Engineering, or equivalent area

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.

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