Jobs in the United States

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Added 3 hours ago
ST
Process Engineer, Chemical and Mechanical Polish (CMP)
Skorpios Technologies, Inc.
Temecula, CA
- $100,000 to $140,000 USD / year
…failure for yield loss and improving quality. The CMP Process Development Engineer will interact with Senior Process Development Engineers, Product Design and Process Integration personnel…
Added 5 days ago
Director, Quality Engineering
SI-BONE, Inc
San Jose, CA
The Director of Quality Engineering leads the technical quality function supporting product development, manufacturing, suppliers, and sustaining engineering. The Director manages the…
Added 6 days ago
Associate Process Engineer
The Boeing Company
Sylmar, CA
Experience with gated approach to process and product development and Aerospace industry material and qualification requirements
Added 7 days ago
M
Principal Product Engineer
Microsoft
WA · CA · TX · OR · Redmond, WA · Mountain View, CA · Austin, TX · Hillsboro, OR · Redmond · Mountain View · Austin · Hillsboro
- $142,800 to $304,200 USD / year
We are looking for a Principal Product Engineer to join the team.
Added 8 days ago
K
Mid-Level or Senior IC Product Engineer
Kforce
Chandler, AZ
- $120,000 to $155,000 USD / year
The Mid-Level or Senior IC Product Engineer will play a key role in bringing new semiconductor products from concept to production. This position is responsible for first silicon…
Added 9 days ago
Senior Principal Engineer, Hardware Application Engineering - Signal Integrity & Power Integrity
MSI - (Marvell Semiconductor Inc.) US
Santa Clara, CA
As Senior Principal Engineer for Signal Integrity and Power Integrity, you will be the senior technical authority responsible for ensuring that customer platforms built on Marvell's…
Added 10 days ago
Silicon Packaging Engineer (SIPI)
Meta
Menlo Park, CA · Sunnyvale, CA
We are seeking a highly skilled Signal Integrity and Power Integrity (SI/PI) Engineer to own chip-package-system co-design for next-generation AI accelerator and high-performance computing…
Added 11 days ago
Validation Engineer
Nexperia USA
United States
Lead the bench validation activity of silicon ICs during the product development.
Added 13 days ago
Silicon Packaging Engineer (SIPI)
Meta
Sunnyvale, CA · Menlo Park, CA
We are seeking a highly skilled Signal Integrity and Power Integrity (SI/PI) Engineer to own chip-package-system co-design for next-generation AI accelerator and high-performance computing…
Added 16 days ago
Signal and Power Integrity Engineer
Google
Sunnyvale, CA
Experience with lab bring-up, test environments, and characterization for high-speed memory and SerDes.
Added 17 days ago
Signal Integrity & Power Integrity Engineer - Los Altos
Majestic Labs
Los Altos, CA
We are looking for a Senior Signal Integrity (SI) and Power Integrity (PI) Engineer to own end-to-end electrical link performance across our high-speed interconnects - from architecture and…
Added 17 days ago
Systems Engineering Analog IC Validation
LSI Corporation
United States
Work in parallel with Firmware development, High-speed I/O designers, and Digital IC design teams as part of the pre/post-silicon validation process
Added 17 days ago
MT
Principal Signal Integrity Engineer, Pathfinding
Micron Technology
Boise · Folsom · Richardson · San Jose
- $119,000 to $320,000 USD / year
As a Principal Signal Integrity Engineer, you will be a core technical contributor on a deliberately small, senior team united around the goal of preparing high-speed interface innovations…
Added 17 days ago
Principal Signal Integrity Engineer
Micron Technology
Boise · Richardson
As a Principal Signal Integrity Engineer, you will be a core technical contributor on a deliberately small, senior team united around the goal of preparing high-speed interface innovations…
Added 18 days ago
R
Sr. Staff Electronic Design Engineer (ADAS Hardware)
Rivian
Palo Alto, CA
- $213,000 to $266,000 USD / year
…from concept through production and beyond. Beyond initial development, you will serve as a technical anchor for the company, leading the debugging of field issues and navigating supply…
Added 19 days ago
Senior High-Speed PCB Engineer - TeraWave
Blue Origin Personnel, LLC
United States
Perform pre- and post-layout signal integrity (SI) analysis, including SerDes lanes, DDR memory buses, and high-density Ethernet switch interconnects.
Added 20 days ago
Senior Product Development Engineer - Boards
NVIDIA USA
CA
NVIDIA is an industry leader in AI, high performance computing and gaming. We are the Board Product Development Engineering team within NVIDIA’s operations group. Our work lies at the…
Added 20 days ago
Senior System Integration Engineer, Memory
NVIDIA USA
Remote, United States
NVIDIA's Silicon Co-Design Group (SCG) leads the full product development lifecycle, from early architecture definition through silicon bringup to product release. The ArchDev team is the…
Added 20 days ago
S
Principal Audiological Engineer
Starkey
Eden Prairie, MN
- $137,000 to $178,500 USD / year
The Principal Audiological Engineer, Product Development provides technical leadership for translating hearing science, audiology, acoustics, and signal-processing knowledge into…
Added 20 days ago
Principal Post-Silicon Validation Engineer
SambaNova
San Jose, CA
We're the team behind post-silicon bring-up, debug, and validation for the high-speed IO and memory subsystems in SambaNova's DataScale platform. We own the path from first silicon power-on…
Added 20 days ago
Semiconductor Product Engineer, Amazon Leo
Amazon Kuiper Manufacturing Enterprises LLC
Redmond, WA
- 8+ years of experience in post-Si modem product engineering through post-silicon characterization and qualification.
Added 20 days ago
Senior Product Engineer, Product Engineering
Amazon Kuiper Manufacturing Enterprises LLC
Austin, TX · Sunnyvale, CA · Redmond, WA · San Diego, CA
- RF product development and characterization experience.
Added 20 days ago
Systems Engineering Analog IC Validation
LSI Corporation
United States
Work in parallel with Firmware development, High-speed I/O designers, and Digital IC design teams as part of the pre/post-silicon validation process
Added 20 days ago
Power Electronics Application Engineer
PHIHONG USA
Fremont, CA
Provide feedback on customer requirements for future product development.
Added 20 days ago
Silicon Photonics Design & Test Engineer
Nokia
United States
Are you a passionate Silicon Photonics Design Engineer eager to contribute to groundbreaking research and development? Join our team and play a key role in designing and developing…

Silicon Packaging Engineer (SIPI)

Sunnyvale, CA, United States
Menlo Park, CA, United States

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Job details

Experience: 8+ years of experience with signal integrity analysis, simulation, and measurement
Posting language: English
Posted: Sep 18, 2026

Original job description

Summary:

We are seeking a highly skilled Signal Integrity and Power Integrity (SI/PI) Engineer to own chip-package-system co-design for next-generation AI accelerator and high-performance computing silicon. In this role you will drive SI/PI requirements from architecture definition through post-silicon validation across 2.5D/3D heterogeneous packages - silicon interposer, RDL fan-out, wafer-on-wafer die stacking, and high-density organic substrates. You will work closely with ASIC architecture, physical design, package layout, PCB, and foundry/OSAT partners to ensure high-speed interfaces and power delivery networks meet performance, margin, and reliability targets before tape-out and Gerber release.

Required Skills:

Silicon Packaging Engineer (SIPI) Responsibilities:

Chip-Package-System Co-Design: Drive SI/PI requirements analysis and optimization into product definition - chip floorplan, bump map, power tree structure, and net topology - for HPC and AI silicon built on 2.5D/3D package technology.
Die-Package-Board Co-Optimization (DPCO): Partner with package layout and physical design to converge bump assignment, escape routing, and stack-up decisions across multiple disparate chiplets.
Package SI/PI Ownership: Lead ASIC package SI/PI design activities including substrate and interposer stack-up and material selection, design guide authoring, layout review, and post-layout sign-off.
High-Speed Interfaces: Own channel design and margining for HBM/HBM4/UHBM, UCIe and other die-to-die links, PCIe Gen 5/Gen 6, Ethernet SerDes, and next-generation memory interfaces.
Power Delivery: Execute package and board PDN AC+DC analysis for low-voltage/high-current supplies, including impedance targeting, decoupling optimization, IR drop, and di/dt noise.
Simulation Flow: Lead pre-layout and post-layout simulation flows for high-speed I/O and PDN
build simulation models and develop reusable SI/PI methodology.
Timing & Budgets: Develop and maintain interface timing budgets and voltage/noise budgets spanning silicon IO PHY, package, and board.
Tool & Flow Development: Improve the accuracy and turnaround time of SI/PI flows through automation and correlation-driven model refinement.
Validation Methodology: Define SI/PI validation methodology and detailed engineering test plans.
Post-Silicon: Conduct post-silicon validation and qualification of high-speed interfaces
measure PDN impedance and channel performance in the lab and correlate against simulation.
Failure Analysis: Support Design Validation teams on SI/PI failure analysis and drive corrective design guidance back into the flow.
Work across Architecture, ASIC, Mixed Signal, Package, PCB, and System teams to ensure package and system SI/PI performance meets expectation before Gerber out.
Engage foundries and OSATs (e.g., TSMC CoWoS/SoIC, Intel EMIB) and memory suppliers on emerging interconnect and die-stacking standards.

Minimum Qualifications:

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
8+ years of experience with signal integrity analysis, simulation, and measurement
Proficient with HFSS, Sigrity, Hspice, and/or other simulation tools
Proven understanding of impedance control, transmission line and PDN characterization, feasibility study and create practical design guidelines
Experience with 2.5D/3D package design (e.g., silicon interposer, silicon bridge, 3D die stacking, STA, Voltage budget, complex SIPI models, frequency, and time domain simulation)
Expertise in signal and power integrity for various high speed interconnects (e.g., HBMx, D2D, Ethernet, PCIe and etc)
Familiarity with post-Si test environment on memory (HBM/ /DDR4/LPDDR4/DDR5/LPDDR5) or high speed SERDES
Familiarity to next generation memory and chiplet standards and timing budget methodology
Package-level signal integrity and power integrity understanding including silicon, package, and board

Preferred Qualifications:

10+ years of experience in SIPI simulation and validation areas
Master degree or PhD in Electrical Engineering, Physics, Mathematics, or related field
Experience with high-speed interface protocols such as MIPI, PCIe, memory, HBMand USB
Experience using Cadence Sigrity, PowerSI, Ansys SIwave, Keysight ADS, 3D layout and Ansys HFSS
Experience with consumer hardware design, review and bring-up process, CAD tools, constraint manager etc
8+ years of experience in SIPI fundamentals, familiar with substrate/PCB design and manufacture process
Experience in collaborating with cross-functional teams, including chip top design, physical design, Static Timing Analysis (STA), package, and system teams
Solid understanding and experiences in computational electromagnetics and transmission line theory

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.

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Skills

Packaging
Printed circuit boards
Computer science
Computer engineering
Electrical engineering
Ansys
Design hardware

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