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Added 3 days ago
Principal Analog Design Engineer
Micron Technology, Inc.
Richardson, TX
We are seeking a Principal Analog Design Engineer to lead the design, integration, and delivery of advanced analog and mixed-signal IPs for High Bandwidth Memory (HBM) products. This role…
Added 6 days ago
TI
ASIC RTL/SoC Design Engineer
TETRAMEM INC
San Jose, CA
- $110,000 to $300,000 USD / year
Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs
Added 9 days ago
I
Pre-Si Power Performance Val & Opt Engineer (Contract)
Intel
Hillsboro, OR
- $52,000 to $200,000 USD / year
You will be joining Intel's Data Center Group (DCG), a team dedicated to advancing data-centric technologies and solutions that power the world's digital infrastructure. The group focuses…
Added 9 days ago
M
Principal Product Engineer
Microsoft
WA · CA · TX · OR · Redmond, WA · Mountain View, CA · Austin, TX · Hillsboro, OR · Redmond · Mountain View · Austin · Hillsboro
- $142,800 to $304,200 USD / year
Drive pre-Si readiness for power, performance, Thermal and Power delivery (LDOs, Integrated VRs) related tests and features for successful bring up during power on. Drive Power and…
Added 10 days ago
Senior Hardware Design Engineer - PCB Design
General Motors LLC
Warren, MI · Sunnyvale, CA
Create / collaborate closely with other design teams, such as circuit designers, system engineers, and packaging engineers, to understand design requirements and constraints. They work…
Added 11 days ago
Principal Electrical Engineer
Oracle
Santa Clara, CA
Designs, develops, and integrates complex electrical systems for hardware products, ensuring they meet functional, performance, power efficiency, security, and reliability requirements.…
Added 11 days ago
ASIC Packaging Signal/Power Integrity Hardware Engineer (Hybrid)
Cisco Systems, Inc.
San Jose, CA
We are seeking a qualified Signal and Power Integrity Engineer to help us develop our next generation ASIC packaging to help define, design and verify ASIC packaging to be deployed in a…
Added 12 days ago
Silicon Packaging Engineer (SIPI)
Meta
Menlo Park, CA · Sunnyvale, CA
We are seeking a highly skilled Signal Integrity and Power Integrity (SI/PI) Engineer to own chip-package-system co-design for next-generation AI accelerator and high-performance computing…
Added 14 days ago
Senior Hardware Engineer: Connectivity Modules
General Motors
Sunnyvale, CA
The Senior Hardware Engineer will lead the design, architecture, and system integration of connectivity modules across GM vehicle platforms. This includes defining system architecture,…
Added 14 days ago
Staff Hardware Engineer: Connectivity Platforms
General Motors
Sunnyvale, CA
The Staff Hardware Engineer will own the system architecture and technical direction for connectivity modules across multiple vehicle platforms. This includes defining scalable…
Added 15 days ago
Silicon Packaging Engineer (SIPI)
Meta
Sunnyvale, CA · Menlo Park, CA
We are seeking a highly skilled Signal Integrity and Power Integrity (SI/PI) Engineer to own chip-package-system co-design for next-generation AI accelerator and high-performance computing…
Added 15 days ago
Senior Staff Applications Engineer
Altium
Austin, TX
As a Senior Staff Application Engineer for the Renesas Performance Computing Power Emulation Engineering team, you will be part of a fast-paced power management team supporting pre-silicon…
Added 16 days ago
Senior Hardware Design Engineer
Broadata Communications
Torrance, CA
We are seeking a hands-on Senior Hardware Design Engineer to design, simulate, bring up, and validate complex mixed-signal and high-speed digital hardware for BCI multimedia, video-over-IP,…
Added 17 days ago
Senior Staff Engineer Field Application Engineering
Infineon
Washington · Andover
…integration. Drawing on Infineon's portfolio of radiation-hardened and radiation-tolerant semiconductors - MOSFETs, GaN power devices, gate drivers, and integrated power ICs - you will…
Added 17 days ago
Principal Analog Design Engineer
Micron Technology
Richardson
We are seeking a Principal Analog Design Engineer to lead the design, integration, and delivery of advanced analog and mixed-signal IPs for High Bandwidth Memory (HBM) products. This role…
Added 17 days ago
Simulation Engineer & Computational Modeling
CADFEM India Pvt Ltd
Lake Forest, CA
on SI/PI, electromagnetic analysis, and system-level modeling to evaluate and optimize product performance, reliability, and
Added 18 days ago
Signal Integrity & Power Integrity Engineer - Los Altos
Majestic Labs
Los Altos, CA
We are looking for a Senior Signal Integrity (SI) and Power Integrity (PI) Engineer to own end-to-end electrical link performance across our high-speed interconnects - from architecture and…
Added 18 days ago
Senior mixed-signal electrical engineer (Board Level)
ASML US, LP. (US31)
San Jose, CA
Perform modeling, simulation, and performance validation:
Added 19 days ago
Principal Analog Design Engineer, HBM
Micron Technology
Richardson
We are seeking a Principal Analog Design Engineer to lead the design, integration, and delivery of advanced analog and mixed-signal IPs for High Bandwidth Memory (HBM) products. This role…
Added 19 days ago
MT
Principal Signal Integrity Engineer, Pathfinding
Micron Technology
Boise · Folsom · Richardson · San Jose
- $119,000 to $320,000 USD / year
Design Rule Development - Driving progressive design rules that enable package and system-level performance scaling
Added 19 days ago
Principal Signal Integrity Engineer
Micron Technology
Boise · Richardson
Design Rule Development - Driving progressive design rules that enable package and system-level performance scaling
Added 20 days ago
Advanced Power Integrity & Power Delivery Architect
Rivian
Palo Alto, CA
We are seeking a highly skilled and motivated Power Integrity & Power Architecture Engineer to lead the end-to-end design, modeling, simulation, and post-silicon validation of advanced SoC…
Added 20 days ago
V
SI/PI Engineer
Vinci
Palo Alto, CA
- $160,000 to $200,000 USD / year
- Assess system-level SI/PI performance and correlate Vinci results against industry-standard EM and circuit simulation tools.
Added 21 days ago
Sr Solutions Engineer-FPGA/PCIe
Advanced Micro Devices, Inc
San Jose, CA
You are passionate about modern processor architecture, digital design, and system-level validation. You thrive in collaborative environments, communicate effectively across global teams,…
Added 21 days ago
SerDes Application Design Expert
Advanced Micro Devices, Inc
San Jose, CA
You are a self-motivated engineer with strong system intuition and a hands-on mindset, equally comfortable working close to hardware and collaborating across firmware, electrical, and…

Silicon Packaging Engineer (SIPI)

Sunnyvale, CA, United States
Menlo Park, CA, United States

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Job details

Experience: 8+ years of experience with signal integrity analysis, simulation, and measurement
Posting language: English
Posted: Sep 18, 2026

Original job description

Summary:

We are seeking a highly skilled Signal Integrity and Power Integrity (SI/PI) Engineer to own chip-package-system co-design for next-generation AI accelerator and high-performance computing silicon. In this role you will drive SI/PI requirements from architecture definition through post-silicon validation across 2.5D/3D heterogeneous packages - silicon interposer, RDL fan-out, wafer-on-wafer die stacking, and high-density organic substrates. You will work closely with ASIC architecture, physical design, package layout, PCB, and foundry/OSAT partners to ensure high-speed interfaces and power delivery networks meet performance, margin, and reliability targets before tape-out and Gerber release.

Required Skills:

Silicon Packaging Engineer (SIPI) Responsibilities:

Chip-Package-System Co-Design: Drive SI/PI requirements analysis and optimization into product definition - chip floorplan, bump map, power tree structure, and net topology - for HPC and AI silicon built on 2.5D/3D package technology.
Die-Package-Board Co-Optimization (DPCO): Partner with package layout and physical design to converge bump assignment, escape routing, and stack-up decisions across multiple disparate chiplets.
Package SI/PI Ownership: Lead ASIC package SI/PI design activities including substrate and interposer stack-up and material selection, design guide authoring, layout review, and post-layout sign-off.
High-Speed Interfaces: Own channel design and margining for HBM/HBM4/UHBM, UCIe and other die-to-die links, PCIe Gen 5/Gen 6, Ethernet SerDes, and next-generation memory interfaces.
Power Delivery: Execute package and board PDN AC+DC analysis for low-voltage/high-current supplies, including impedance targeting, decoupling optimization, IR drop, and di/dt noise.
Simulation Flow: Lead pre-layout and post-layout simulation flows for high-speed I/O and PDN
build simulation models and develop reusable SI/PI methodology.
Timing & Budgets: Develop and maintain interface timing budgets and voltage/noise budgets spanning silicon IO PHY, package, and board.
Tool & Flow Development: Improve the accuracy and turnaround time of SI/PI flows through automation and correlation-driven model refinement.
Validation Methodology: Define SI/PI validation methodology and detailed engineering test plans.
Post-Silicon: Conduct post-silicon validation and qualification of high-speed interfaces
measure PDN impedance and channel performance in the lab and correlate against simulation.
Failure Analysis: Support Design Validation teams on SI/PI failure analysis and drive corrective design guidance back into the flow.
Work across Architecture, ASIC, Mixed Signal, Package, PCB, and System teams to ensure package and system SI/PI performance meets expectation before Gerber out.
Engage foundries and OSATs (e.g., TSMC CoWoS/SoIC, Intel EMIB) and memory suppliers on emerging interconnect and die-stacking standards.

Minimum Qualifications:

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
8+ years of experience with signal integrity analysis, simulation, and measurement
Proficient with HFSS, Sigrity, Hspice, and/or other simulation tools
Proven understanding of impedance control, transmission line and PDN characterization, feasibility study and create practical design guidelines
Experience with 2.5D/3D package design (e.g., silicon interposer, silicon bridge, 3D die stacking, STA, Voltage budget, complex SIPI models, frequency, and time domain simulation)
Expertise in signal and power integrity for various high speed interconnects (e.g., HBMx, D2D, Ethernet, PCIe and etc)
Familiarity with post-Si test environment on memory (HBM/ /DDR4/LPDDR4/DDR5/LPDDR5) or high speed SERDES
Familiarity to next generation memory and chiplet standards and timing budget methodology
Package-level signal integrity and power integrity understanding including silicon, package, and board

Preferred Qualifications:

10+ years of experience in SIPI simulation and validation areas
Master degree or PhD in Electrical Engineering, Physics, Mathematics, or related field
Experience with high-speed interface protocols such as MIPI, PCIe, memory, HBMand USB
Experience using Cadence Sigrity, PowerSI, Ansys SIwave, Keysight ADS, 3D layout and Ansys HFSS
Experience with consumer hardware design, review and bring-up process, CAD tools, constraint manager etc
8+ years of experience in SIPI fundamentals, familiar with substrate/PCB design and manufacture process
Experience in collaborating with cross-functional teams, including chip top design, physical design, Static Timing Analysis (STA), package, and system teams
Solid understanding and experiences in computational electromagnetics and transmission line theory

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.

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Skills

Packaging
Printed circuit boards
Computer science
Computer engineering
Electrical engineering
Ansys
Design hardware

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