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Automation Engineer 4 (SDET/API automation)
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Design Verification Engineer - Accelerators

Redmond, WA, United States

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Job details

Experience: 8+ years of hands-on verification experience with SystemVerilog, UVM and C/C++ at the IP, subsystem and SoC level
Posting language: English
Posted: Nov 3, 2026

Original job description

Summary:

The AR glasses Meta is building run on custom silicon that delivers serious compute within a tight power budget. Our silicon team designs that silicon, with breakthrough work in computer vision, machine learning, imaging, and sensing. We're hiring a Design Verification (DV) lead to own verification for complex computer vision and imaging accelerator IP and subsystems. In this role, you'll define the verification strategy across multiple IPs and build DV infrastructure that scales across chips and programs.

Required Skills:

Design Verification Engineer - Accelerators Responsibilities:

Shape architecture and microarchitecture decisions with architects, design, FW/SW, emulation, physical design and post-silicon teams so the chip is designed with verification in mind. Work with TPMs on schedules and sign-off criteria
Own DV for multiple complex IPs or subsystems from start to finish, all the way from verification planning through coverage closure and sign-off
Define the strategy across IPs, including the mix of simulation (constrained-random, UVM), formal, assertions, emulation and FPGA prototyping, plus power-aware verification (UPF)
Design reusable testbench architectures, verification IP and libraries that are shared across IPs, subsystems and SoC generations
Drive regression management, automated triage, coverage analytics, and compute-efficient runs (simulation and emulation) so the team can sustain high throughput as the number of designs grows
Spot verification-quality and productivity gaps across the org, lead initiatives that measurably improve quality and time-to-closure, and drive DV methodology improvements, including AI-assisted ones
Root-cause failures down to specific lines of RTL, reference model or FW/SW, and propose the fixes

Minimum Qualifications:

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
8+ years of hands-on verification experience with SystemVerilog, UVM and C/C++ at the IP, subsystem and SoC level
Has led DV for complex IP or an SoC through tape-out, including owning sign-off
Has defined and run verification plans, coverage strategies, and closure metrics (functional and code coverage) across multiple blocks or IPs
Has built UVM verification environments from scratch and designed reusable verification components
Deep experience in at least one of: formal verification, SystemVerilog Assertions (SVA), emulation/FPGA prototyping, or low-power (UPF) verification
Strong scripting skills (Python, TCL, Perl, Shell) for building verification tools and flows
Has led and mentored engineers and coordinated work across teams

Preferred Qualifications:

Has verified power-limited mobile, wearable or AR/VR System-on-Chips (SoCs)
Has managed EDA vendors or contracted DV teams
Has verified computer vision, imaging/ISP, DSP or ML accelerator designs
Master's or PhD in EE/CE/CS
Has rolled out methodology changes (formal, emulation, portable stimulus, ML/AI-assisted verification) across an org
Has verified hardware against reference models written in C++ or Python, or co-simulated with firmware or software
Has scaled DV infrastructure (regression farms, CI for hardware, coverage and triage dashboards) across multiple IPs or programs

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.

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Skills

RTL
Computer science
Computer engineering
Electrical engineering
SystemVerilog
C
Python
Perl
EDA
ML
C++
Firmware

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