Senior RTL Design

Actalent

Santa Clara, CA

• $200,000 to $500,000 USD / year

Job Title: Senior RTL Design EngineerJob DescriptionWe are seeking a highly skilled Senior RTL Design Engineer to join our team. You will play a pivotal role in designing, implementing, and…

Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team

Amazon

Austin, TX

Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and…

Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration - Annapurna Labs

Amazon

Austin, TX

Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and…

AI Systems Engineer, Hardware Architecture

Meta

Dover, DE

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Washington, DC

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Phoenix, AZ

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Hartford, CT

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Cheyenne, WY

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Charleston, WV

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Richmond, VA

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Lansing, MI

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Nashville, TN

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Santa Fe, NM

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Concord, NH

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Trenton, NJ

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Columbia, SC

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Lincoln, NE

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Boise, ID

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Bismarck, ND

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Boston, MA

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Pierre, SD

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Annapolis, MD

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Jackson, MS

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Honolulu, HI

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation

AI Systems Engineer, Hardware Architecture

Meta

Saint Paul, MN

Familiarity with custom silicon development flows for imaging and AI accelerators, including architecture-to-RTL handoff, physical design constraints, and post-silicon validation