R&D Engineer IC Design

Work on Design Implementation activities related to complex digital and mixed signal IP blocks used in the development of Broadcom’s ASIC / SoC products. Activities include constraints development, constraints verification, deployment of SDF, extracted timing models and timing closure. Required to do block-level synthesis, verification (static, formal) and place and route related activities. Work closely with the IP and SOC design teams to enable block and ASIC level timing closure. Work with the internal ASIC / SoC teams and Broadcom customers to support constraints, timing analysis, timing closure, and physical implementation involving the IP blocks. Developing SDF's and ETM's for various IP blocks. Debugging customer problems involving the use of these IP deliverables. Will be exposed to various IP and ASIC / SoC developments. Opportunities for customer interaction and other high profile activities are available to members of this team. Apply Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon.

Ref job code C#10016436 & email resume to: submit.apps@broadcom.com. EOE. Must include ref code.

Requirements:

Bachelor’s degree or foreign degree equivalent in Electrical and Computer Engineering, or related field. 8 years of post-baccalaureate, progressive experience in the R&D Engineer IC Design, or any other related occupation, job title/position.