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  • SoC Physical Design Engineer, Electrical Analysis

    Apple

    San Diego, CA

    Experience with ASIC or AMS physical implementation and analysis flow for IP blocks as well as SoC fullchip.

  • SoC Physical Design Engineer, Electrical Analysis

    Apple

    Austin, TX · San Jose, CA

    Experience with ASIC or AMS physical implementation and analysis flow for IP blocks as well as SoC fullchip.

  • Senior DFT Logic Design Engineer

    Intel Corporation

    AZ · CA · OR

    • $141,910 to $269,100 USD / year

    Hands-on experience in one or more areas of Design Implementation and methodology - (ASIC design, Fullchip Integration, Design Signoff, LVS, DRC, DFX/DFM, Reliability, etc).

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