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  • Senior SoC Design Engineer

    Microsoft

    CA · Mountain View, CA

    • $119,800 to $261,000 USD / year

    You will be part of the SOC design team driving many facets of high performance, high bandwidth designs. The tasks will include working on Intellectual Property (IP) microarchitecture…

  • Staff Engineer, SoC Emulation & Prototyping

    Advanced Micro Devices, Inc

    San Jose, CA

    The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.

  • Staff Hardware Engineer, Optics

    MSI - (Marvell Semiconductor Inc.) US

    Santa Clara, CA

    Design the hardware you’ll bring up. Translate platform requirements into schematics, component selections, and PCB layout constraints for power delivery, clocking, control interfaces, and…

  • Senior RTL Design Engineer, TPU

    Google

    Sunnyvale, CA

    In this role, you will join a team working on SoC-level RTL design for our data center accelerators. You will design RTL Intellectual Property (IP) with the focus on management and control…

  • Physical Design Clocking Engineer

    Intel

    Santa Clara, CA

    • $105,650 to $149,150 USD / year

    As a Physical Design Engineer, you will play a critical role in the implementation of custom IP and SoC designs, transforming RTL to GDS to produce design databases ready for manufacturing.…

  • SoC Silicon Top-Level Floorplan Engineer

    Google

    Sunnyvale, CA

    Experience in SoC Integrated Circuit (IC) design including multi-die partitioning, optimizing performance, power, and area (PPA), and physical verification.

  • Director, Payload Electronics, Space Communications Systems

    E-Space

    Santa Clara, CA · Saratoga, CA

    • $200,000 to $290,000 USD / year

    …orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT…

  • Senior Mixed Signal Post Silicon Validation Engineer IOs

    Intel Corporation

    CA

    • $141,910 to $200,340 USD / year

    …versatile team of engineers who directly engage with both IP design teams and SOC customers in IP validation and debug for test chips and products. These engineers embody our SOC customer…

  • RTL Design Engineer, Google Cloud - Sunnyvale

    Google

    Sunnyvale, CA

    2 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development.

  • Design/SDC Engineer

    Inabia Software & Consulting Inc.

    San Jose, CA

    You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in…

  • ASIC Emulation and Verification Engineer

    Broadcom

    San Jose, CA

    Job Title: ASIC Emulation & Verification Engineer (Palladium Specialist)

  • ASIC Physical Design, Principal Engineer

    Synopsys

    Sunnyvale, CA

    You can explain a complex physical design tradeoff to an analog engineer, a front-end architect, and a customer program manager, and have all three understand what matters to them

  • Senior Electrical Engineer, Robot Controller Hardware

    Dexmate

    Fremont, CA

    We are looking for a Senior Electrical Engineer to design the onboard controller hardware for Dexmate’s robot platforms. You will own multi-processor architectures integrating NVIDIA Jetson…

  • Electrical Engineer (Prism)

    Northwood Space

    Los Angeles, CA, CA

    • $125,000 to $145,000 USD / year

    Northwood is looking for an Electrical Engineer to own the non-RF electronics design for Prism, our 2.4-meter parabolic antenna for high-throughput satellite links. You will design the…

  • Senior/Lead VLS Engineer - Global Circuits

    SambaNova

    San Jose, CA

    We are looking for a Senior / Lead VLSI Design Engineer to serve as the architect and hands-on owner for various global circuit areas including custom clocking, low-power design technqiues…

  • SoC Design Engineer

    Solidigm

    San Jose, CA

    • $167,360 to $267,800 USD / year

    We are seeking an experienced RTL Design Engineer to drive the architecture, design, implementation, and optimization of complex digital logic for next-generation NAND Flash memory–based…

  • Physical Design and Verification Engineer

    Neuralink

    South San Francisco, CA · Fremont, CA

    We are seeking a Senior Physical Design Engineer to own block-to-full-chip implementation and signoff on advanced-node, multi-die 3DIC products. You will drive hierarchical physical design…

  • Physical Design Engineer

    Apple

    Cupertino, CA

    • $174,149 to $225,300 USD / year

    …locations throughout the USA. Collaborating with the logic design team to understand partition architecture and proactively addressing physical design aspects early in the development…

  • Sr Staff Engineer-DFT

    MSI - (Marvell Semiconductor Inc.) US

    Santa Clara, CA

    …Vietnam, and Argentina - and we are looking for a senior staff DFT engineer in Santa Clara on our next-generation ODSP program, to help set up the methodology and flow on our flagship…

  • Senior Lead Design Engineer - RTL Design

    Altera Corporation

    San Jose, CA

    Define design specifications, interface contracts, clocking and reset strategies, performance targets, and implementation plans that align architecture, verification, physical design,…

  • Analog Design Engineer (TERADYNE, Agoura Hills, CA)

    Teradyne

    Agoura Hills, CA

    Teradyne’s Semiconductor Test Division in Agoura Hills, CA is seeking an Analog Design Engineer to contribute to the development of high-speed analog and mixed-signal ASICs for Automatic…

  • ASIC Design/SDC Engineer

    Inabia Software & Consulting Inc.

    San Jose, CA

    You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in…

  • Principal PCS/PMA RTL Design Engineer

    Astera Labs

    San Jose, CA · CA

    Astera Labs is seeking a Principal PCS/PMA RTL Design Engineer to join our San Jose design team, focused on the Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) logic for…

  • Senior Electrical Engineer (Prism)

    Northwood Space

    Los Angeles, CA, CA

    • $150,000 to $225,000 USD / year

    Northwood is looking for a Senior Electrical Engineer to own the non-RF electronics design for Prism, our 2.4-meter parabolic antenna for high-throughput satellite links. You will design…

  • Senior DFT Design Engineer

    Intel Corporation

    CA

    • $141,910 to $172,860 USD / year

    You must possess the below minimum qualifications to be initially considered for this position

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