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DFT Engineer

Tenstorrent

Santa Clara, CA

…team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration,…

Physical Designer Engineer, Synthesis/PnR

Rivian

Palo Alto, CA

…it for future generations. Role Summary As a Physical Design Engineer, you will contribute to all design phases of physical design of high performance SoC design at both the block and…

Principal Engineer (8009)

TSMC

San Jose, CA

• $218,899 to $220,000 USD / year

…Integrated-circuits) design to participate in the chip physical design and implementation for TSMC’s advanced processing technology, including block level floor plan, clock tree synthesis,…

SoC Infrastructure/NoC, Power & Performance Validation Engineer

Qualcomm Technologies, Inc.

Santa Clara, CA

Thorough understanding of CPU and DDR concepts, Mumtimedia, GPU, Peripheral,

CPU Physical Design and Integration Engineer

Apple

Santa Clara, CA

As a CPU Physical Design and Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development.

Graphics FE Integration Engineer

Apple

Santa Clara, CA

- Ensure implementation readiness with RTL lint, custom checks, unit level synthesis and clock/reset/power domain crossing checks.

CPU Clock Implementation Engineer

Apple

Santa Clara, CA

Apple’s Silicon Engineering Group (SEG) is hiring skilled engineers for CPU. As a CPU Clock Implementation Engineer, you will be driving the planning, design, implementation, and analysis…

CPU Clock Implementation Engineer

Apple

Santa Clara, CA

Apple’s Silicon Engineering Group (SEG) is hiring skilled engineers for CPU. As a CPU Clock Implementation Engineer, you will be driving the planning, design, implementation, and analysis…

CPU Design Timing Engineer

Apple

Santa Clara, CA

As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project.

Next Gen CPU Power Management RTL Design Engineer

Advanced Micro Devices, Inc

Santa Clara, CA

Experience with low-power design strategies such as clock gating, power gating, DVFS, and multi-voltage domain implementation.

Senior IC Layout design Engineer

Advanced Micro Devices, Inc

San Jose, CA

…currently seeking an experience analog/mixed-signal layout design engineer with supervisory role to join our world-class team in the development of SerDes solutions to facilitate the future…

Physical Design Engineer

Altera Corporation

San Jose, CA

We are seeking a Physical Design Engineer to join our Silicon Engineering and Physical Design organization. In this role, you will be responsible for implementing advanced custom IP and SoC…

Sr. ASIC Design Engineer (Silicon Engineering)

SpaceX

Palo Alto, CA

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation,…

CPU Power-Management Design Engineer

SiFive, Inc.

Santa Clara, CA

As a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores…

Power Management Design Engineer

SiFive, Inc.

Santa Clara, CA

As a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores…

Power Management Design Engineer

SiFive, Inc.

Santa Clara, CA

As a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores…

Power Management Design Engineer

SiFive, Inc.

Santa Clara, CA

As a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores…

Top Level Physical Design Engineer

Tenstorrent

Santa Clara, CA

Tenstorrent is seeking an exceptional Senior-level Physical Design Engineer to drive top-level implementation of our complex AI and CPU System-on-Chip designs. You'll orchestrate…

Physical Design Engineer, PnR

Tenstorrent

Santa Clara, CA

…UART), signoff breadth (DRC/LVS, EM/IR, LEC/Formality), multi-clock/CDC-aware implementation, PLL/DLL integration, and DFT-aware physical implementation…

CPU Digital Design Engineer

Baidu USA

Sunnyvale, CA

- At least 3 years of CPU related Architect/RTL/Verification/Implementation design experience

CPU Physical Design (RTL Feasibility)

NUVACORE

Santa Clara, CA

• $140,000 to $250,000 USD / year

As a CPU Physical Design (PD) Engineer, you will participate in the following :

CPU Custom Library Cell Design (IC)

NUVACORE

Santa Clara, CA

• $140,000 to $250,000 USD / year

The next great CPU won't build itself. We’re assembling a world-class team across every layer of CPU development, from architecture and design to verification, physical implementation,…