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Added 7 mins ago
Associate Software Engineer - Hollywood (MD)
CORP-Corporate Office
United States
Northrop Grumman is seeking an Associate Software Engineer. This position will be located at our Defense Systems Sector in Hollywood, MD.
Added 7 mins ago
Radiation Systems Engineer - Level 3 or 4 (AHT)
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Added 8 mins ago
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Senior Data Scientist
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Identify and engineer relevant features from text data to improve model performance.
Added 24 mins ago
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Added 24 mins ago
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Added 32 mins ago
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The Operations Service Center Facilities Support Engineer I (FSE) will be primarily responsible for all facilities’ major incident management, monitoring a dashboard for EMPS/BMS alarms,…
Added 35 mins ago
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…in the world with the Cisco portfolio powered by the Splunk Data Platform, our team is poised to lead the market and set the standard for AI…
Added 35 mins ago
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Added 35 mins ago
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Remote, United States
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Added 36 mins ago
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Software QA Engineer II (Full Time) - United States
Cisco
Richardson, TX · San Jose, CA · Milpitas, CA
- Full-time
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Added 36 mins ago
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Software QA Engineer I (Full Time) - United States
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Richardson, TX
- Full-time
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Added 36 mins ago
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Added 37 mins ago
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Added 37 mins ago
Cybersecurity Information Security Assessor
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Added 37 mins ago
Circuit Activation Engineer - TS/SCI clearance
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United States
We’re seeking a Circuit Activation Engineer to design, deploy, and support secure, high‑performance network solutions that keep our mission moving. If you enjoy solving complex technical…
Added 37 mins ago
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Added 37 mins ago
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Added 37 mins ago
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Added 45 mins ago
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The Senior Business Intelligence Engineer solves complex business problems and issues using data from internal and external sources to provide insight to decision-makers. The Senior…
Added 46 mins ago
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Intel

Senior Static Timing Analysis (STA) Engineer

Phoenix, AZ, United States

$164,470 to $269,100 USD / year

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Job details

Pay: $164,470 to $269,100 USD / year
Posting language: English
Posted: Sep 2, 2026

Original job description

Job Details:

Job Description:

Shape the Future of Computing at Intel

Intel is seeking an experienced Senior Static Timing Analysis (STA) Engineer to help drive the development of next-generation semiconductor products. In this role, you will play a critical part in delivering high-performance, power-efficient System-on-Chip (SoC) designs that power industry-leading technologies.

You will work across architecture, logic design, clocking, DFT, and physical design teams to ensure successful timing convergence, signal integrity, performance optimization, and product readiness. This position offers an exciting opportunity to solve complex engineering challenges while influencing methodologies and best practices used across advanced SoC programs.

Key Responsibilities but not limited to:

Perform SOC level timing analysis and optimization, ensuring designs meet functional and performance requirements.
Generate and verify timing constraints while addressing timing violations at the chip or block level for SoCs.
Conduct timing rollups and develop optimized clock networks for functionality, performance, and power efficiency.
Define methodologies to produce high-quality timing models and enable efficient physical design execution.
Establish the appropriate process, voltage, and temperature (PVT) conditions for timing analysis, aligning with product plans, and binning strategies.
Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning.
Collaborate with architecture, clocking design, DFT and logic design teams to develop flows for chip integration and validate clock network performance guidelines.
Contribute to the development of tools, flows, and methodologies that enhance SoC physical design and timing processes.

Behavioral Traits We Are Looking For

Technical Leadership: Demonstrates strong engineering judgment and influences technical direction across complex projects.
Ownership and Accountability: Takes responsibility for challenging technical problems and drives them to closure.
Strategic Problem Solving: Applies analytical thinking and data-driven decision-making to solve highly complex design challenges.
Cross-Functional Collaboration: Builds trusted partnerships across architecture, design, validation, DFT, clocking, and physical design teams.
Communication Excellence: Communicates complex technical concepts effectively to technical and non-technical audiences.
Continuous Improvement Mindset: Identifies opportunities to improve methodologies, tools, and engineering efficiency.
Mentorship: Shares knowledge, coaches peers, and contributes to the development of engineering talent.
Adaptability: Thrives in fast-paced environments with evolving priorities and technical challenges.

Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life.

See Intel Benefits (https://www.intel.com/content/www/us/en/jobs/benefits.html) for more details.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Note:

For information on Intel’s immigration sponsorship guidelines, please see

Intel U.S. Immigration Sponsorship Information (https://www.intel.com/content/www/us/en/jobs/hiring.html)

Minimum Qualifications and Experience:

Bachelor's degree in Computer Engineering, Computer Science, or related STEM discipline and 6+ years of industry experience; OR a Master's degree in the same fields and 4+ years of experience.

5+ years of experience the following:

SOC level static timing analysis, clock network design, and timing closure methodologies.
Timing constraint adaptation, physical design knowledge, and optimization techniques.
Industry-standard tools for timing analysis, extraction, and physical design.
TCL scripting and timing budgeting processes.

Preferred Skills/Experience:

A PhD in the same filed and 2+ years of experience.
Demonstrated ability to collaborate across diverse teams and drive innovative solutions for SoC designs.
Knowledge of tools, flows, and methodologies for high-performance physical design.
Experience with SoC clocking methodologies, disciplined execution, and problem-solving in digital design.
DFT architecture knowledge is a strong plus.

Why Join Intel

Join Intel and play a key role in delivering next-generation SoC products that power future computing innovations. You will work across global teams, influence high-impact design decisions, collaborate with leading engineers, and help drive technologies from development through product delivery. This is an opportunity to solve complex technical challenges while contributing to Intel's expanding product roadmap and future growth.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Arizona, Phoenix

Additional Locations:

US, California, Santa Clara

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003) .

Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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