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Added 57 mins ago
Senior Silicon Architect – Cache Coherent Interconnects
NVIDIA Corporation
CA · TX · OR · Santa Clara, CA · Austin, TX · Hillsboro, OR · Santa Clara · Austin · Hillsboro
Knowledge of advanced packaging (TSMC InFO and CoWoS, Intel EMIB), through-silicon via configurations and backside power delivery is preferred, along with Dielet, Interposer, Substrate…
Added 3 hours ago
S
Principal Packaging Engineer
Skyworks
Richardson
- $122,900 to $255,200 USD / year
…maturing next-generation RF system-in-package (SiP), wafer-level packaging (WLP), and heterogeneous integration technologies that enable future radar, communications, and other emerging…
Added 1 day ago
Physical Designer Engineer, Synthesis/PnR
Rivian
Palo Alto, CA
…it for future generations. Role Summary As a Physical Design Engineer, you will contribute to all design phases of physical design of high performance SoC design at both the block and…
Added 1 day ago
Engineer Circuit Design 3 - 3056332
Apex Systems, Inc.
Cincinnati, OH
Job#: 3056332 Job Description: Engineer Circuit Design 3 Location: Cincinnati, Ohio (On-site) Role Overview A professional opportunity is available for a qualified circuit designer to join…
Added 1 day ago
S
Sr. PCB Fabrication Engineer
Skyworks
Richardson
- $86,600 to $182,500 USD / year
Qorvo is looking for a PCB Fabrication Engineer with knowledge in PCB and/or IC Substrate manufacturing process for RF product applications.
Added 2 days ago
A
Engineer Circuit Design 2
Actalent
Cincinnati, OH
- $62 to $70 USD / hour
Job Title: Engineer Circuit Design 2Job DescriptionJoin our dynamic team focused on developing new capabilities for military and intelligence customers worldwide. Our small business culture…
Added 2 days ago
Senior Foundry Development Engineer
AttoTude
Menlo Park, CA
…using ASICs over dielectric waveguides. We work closely with substrate vendors, foundry partners, cable and packaging subcontractors to move these products from development into…
Added 2 days ago
Sr. Signal & Power Integrity Engineer, Annapurna Labs - AI Silicon Packaging
Amazon
Austin, TX
We are seeking a Sr. Signal & Power Integrity Engineer to join our hardware team and drive the SI/PI analysis and optimization of advanced packaging solutions for next-generation machine…
Added 2 days ago
I
Silicon Packaging Design Engineer
Intel
Phoenix, AZ
- $105,650 to $149,150 USD / year
As a Silicon Packaging Design Engineer, you will play a pivotal role in driving the development of advanced substrate designs, contributing to the creation of cutting-edge technology that…
Added 2 days ago
Sr. Process Engineer
Pregis LLC
Conover, NC
We're Not Just in the Packaging Business–We're in the "Wow" Business
Added 3 days ago
Print & Packaging Operations Manager
Hoskinson Biotechnology
Gillette, WY
Hands-on print production experience, typically 5+ years in prepress, print production, labels, or packaging.
Added 3 days ago
S
Principal Systems/Applications Engineer
Skyworks
Richardson
- $122,900 to $255,200 USD / year
…highly motivated and experienced Principal Systems & Application Engineer to define new Motor Control and Drive solutions for industrial, consumer, and automotive markets and to support key…
Added 3 days ago
Sr. Engineer, Package Design
SiTime Corporation
CA
The Senior Semiconductor Package Engineer is responsible for the specification, design, development, and qualification of unique custom packaging technology for SiTime’s revolutionary…
Added 3 days ago
Principal Engineer, Package Design
SiTime Corporation
CA
The Principal Semiconductor Package Engineer is responsible for the specification, design, development, and qualification of unique custom packaging technology for SiTime’s revolutionary…
Added 3 days ago
Director, fcCSP BU (Advanced Packaging Product Engineer)
Tempe, AZ
Daily application of knowledge of semiconductor packaging assembly and substrate technologies across many concurrent development / New Product Introduction (NPI) programs.
Added 4 days ago
Senior Staff Advanced Packaging Design Engineer
MSI - (Marvell Semiconductor Inc.) US
Burlington, VT · Westborough, MA · Chandler, AZ
Extensive experience in substrate and/or board design for advanced packaging technologies.
Added 4 days ago
IC Package Design Engineer
Rivian
Palo Alto, CA · Irvine, CA
…generations. Role Summary We are seeking an IC Package Design Engineer to join our ASIC team. In this role, you will lead the physical layout, modeling, and analysis of advanced…
Added 4 days ago
Design Release Engineer- Soft Trim
Alten USA
Long Beach, CA
Lead or support the engineering, packaging, release, and launch of soft trim components including wrapped panels, seat surrounds, soft-touch IP skins, armrests, and textile-based liners
Added 4 days ago
Packaging Substrate Engineer
Apple
TX · CA
Our Hardware Technology Packaging team invents, designs, develops, and integrates electronic packaging solutions for Apple’s internal and custom external components of hardware for its…
Added 4 days ago
Staff Engineer, Semi Packaging Engineering
Analog Devices Inc.
MA
This role will be responsible for the development of advanced packaging solutions for semiconductor devices across various market segments. The packaging solutions must meet demanding…
Added 6 days ago
Sr. IC Package Design Engineer (Silicon Engineering)
SpaceX
Irvine, CA · Austin, TX
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation,…
Added 6 days ago
Sr. IC Package Design Engineer (Silicon Engineering)
SpaceX
Austin, TX · Irvine, CA
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation,…
Added 6 days ago
I
Packaging Research and Development Engineer
Intel
Phoenix, AZ
- $133,800 to $188,890 USD / year
Substrate Packaging Technology Development (SPTD) is looking for a Packaging Research and Development Engineer to join the Module Engineering Backend Area specifically to be in charge of…
Added 7 days ago
IC
Sort Interface Pathfinding and Development Engineer
Intel Corporation
OR
- $133,800 to $255,200 USD / year
We are seeking a talented and driven Sort Interface Pathfinding and Development Engineer to join our Sort Interface Development team in Oregon. In this high-impact role, you will pioneer…
Added 7 days ago
Package Engineer, Annapurna Labs - AI Silicon Packaging
Amazon
Austin, TX
The Package Technology Development team within Annapurna Labs is building the packaging, substrate/PCB, interposer, and assembly technologies for the next-generation Trainium AI…

Intel

Packaging Research and Development Engineer

Phoenix, AZ, United States

$133,800 to $188,890 USD / year

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Job details

Pay: $133,800 to $188,890 USD / year
Posting language: English
Posted: Sep 11, 2026

Original job description

Job Details:

Job Description:

Substrate Packaging Technology Development (SPTD) is looking for a Packaging Research and Development Engineer to join the Module Engineering Backend Area specifically to be in charge of process and material development to scale advanced substrate packaging technology to enable further die disaggregation / heterogenous integration.

This position requires most of time spent on the factory floor and/or interacting with equipment/material suppliers. The candidate will join and become part of a world class first of a kind embedded die packaging facility, learn advanced substrate manufacturing know-how, drive disruptive technology innovations, and be part of creating history in the substrate packaging industry.

Responsibilities will include but not be limited to:

Define and establish equipment configurations, process specifications, and integrated process flow for new process technologies
Plan and conduct comprehensive DOEs to fundamentally characterize process window, and understand process / equipment / materials interactions
Drive continuous process improvements on process capability/stability, quality/reliability, cost/yield, automation, and productivity
Lead and participate in cross-functional and cross-organizational teams or work groups that support substrate technology development.

The ideal candidate should exhibit the following behavioral traits and/or skills:

Written and verbal communication and teamwork skills.
Interact with equipment and materials suppliers.
Willingness to travel (some travel may be required, less than 5 percent)
Work with ambiguity and flexibility with respect to job roles and working hours is required.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum qualifications:

The candidate must possess one of the following:

Master's degree in a relevant science or engineering discipline, preferably Mechanical Engineering, Chemical Engineering, Materials Science, Physics, or Chemistry , with 3+ years of related experience ; or
PhD degree in a relevant science or engineering discipline, preferably Mechanical Engineering, Chemical Engineering, Materials Science, Physics, or Chemistry , with 1+ year of related experience .

Experience listed below should be in any of the following:

Mechanical & Materials Engineering: Solid background in mechanical and materials engineering, with experience applying materials characterization, mechanical design principles, reliability assessments, and failure analysis to support advanced packaging and manufacturing technology development.
Advanced Packaging & Manufacturing Development: Experience developing semiconductor packaging, substrate, embedded die, or heterogeneous integration technologies, including hands-on work with process equipment, factory operations, and equipment suppliers.
Process Characterization & Optimization: Expertise in DOE, statistical analysis, process development, root cause investigation, and driving improvements in yield, reliability, quality, and process capability.

Preferred qualifications:

1+ years of experience in the following:

Research & Innovation Experience: Experience conducting research in semiconductor packaging, materials, manufacturing processes, or related fields
Engineering troubleshooting and analytical skills on integrated technology issues and experience working with broad team of other process and integration engineers.
Experience owning process tools with knowledge of SPC PCS RFCs equipment troubleshooting statistical design of experiments and process development.
Experience working with a variety of organic/inorganic materials and processes as well as characterizations utilizing techniques such as DSC, TGA, D/TMA, Titration, ICPMS, FTIR, XPS, TOFSIMS, EDX, SEM, etc. is highly desirable.
Experience with statistical data analysis, JMP and JSL, Python, relational database structure and usage, machine learning.

Become part of Intel's innovative team and take the next step in your career by applying today.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Arizona, Phoenix

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003) .

Annual Salary Range for jobs which could be performed in the US: $133,800.00-188,890.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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