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Added 1 day ago
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RTL Design Engineer
Intel
Phoenix, AZ
- $91,150 to $172,860 USD / year
As a CPU Logic Design Engineer, you will play a critical role in shaping Intel's next-generation, high-performance microprocessors. Leveraging your technical expertise, you will contribute…
Added 1 day ago
AM
Sr. Silicon Design Engineer
Advanced Micro Devices
Fort Collins, CO
- $157,463.65 to $182,520 USD / year
Duties: Research, design, develop, and/or test electronic components and systems for semiconductor and related device manufacturing, employing knowledge of electronic theory. Oversee…
Added 1 day ago
CPU Performance Research Engineer
Qualcomm Incorporated
Austin, TX
…help create a smarter, connected future for all. As a Qualcomm CPU Performance Research Engineer, you will drive innovation in next-generation CPU performance, efficiency, and scalability.…
Added 1 day ago
Entry level Hardware Developer - Austin, TX - 2027
IBM
Austin, TX
Design Verification Engineer As a CPU/ASIC Verification Engineer, you will be part of a team that’s responsible for the pre-silicon functional and performance verification of our chipsets.…
Added 2 days ago
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•AI/ML CAD Engineer, RTL & Design Verification
Intel
Hillsboro, OR
- $122,440 to $232,190 USD / year
Join a team helping shape the future of high-performance CPU design. As an AI/ML CAD Engineer supporting RTL and Design Verification , you will develop and enhance automation, tools, and…
Added 2 days ago
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Mid-level Physical Design Engineer CPU
Intel
Hillsboro, OR
- $122,440 to $232,190 USD / year
Join a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Mid-level Physical Design Engineer CPU, you will contribute to delivering…
Added 2 days ago
CPU Core Verification Engineer
Advanced Micro Devices, Inc.
FISHKILL, NY
Added 2 days ago
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CPU Physical Design Engineer
Intel Corporation
TX
- $105,650 to $200,340 USD / year
Join Intel as a CPU Physical Design Engineer and begin your career working on advanced processor technology. In this early-career role, you will work alongside experienced engineers and…
Added 2 days ago
Physical Designer Engineer, Synthesis/PnR
Rivian
Palo Alto, CA
…protect it for future generations. Role Summary As a Physical Design Engineer, you will contribute to all design phases of physical design of high performance SoC design at both the block…
Added 2 days ago
IC
GPU Logic Design Engineer
Intel Corporation
CA
- $141,910 to $200,340 USD / year
As a GPU Logic Design Engineer at Intel, you will play a critical role in shaping the future of graphics and compute technologies. You will be part of a dynamic team driving innovation and…
Added 2 days ago
CPU Core Verification Engineer
Advanced Micro Devices
Fort Collins, CO
Added 2 days ago
Senior Design Verification Engineer
Blue Origin Personnel, LLC
Cupertino, CA
As a Senior Verification Engineer on the ASIC & Networking team, you support TeraWave's first in-house silicon program, which comprises a high-throughput modem and a DSP-intensive digital…
Added 3 days ago
Graphics (GPU) RTL Design Engineer
Apple
Austin, TX
As a GPU Design Engineer, you will be responsible for delivering high-quality, low-power graphics IPs that meet our performance, timing, and area goals. You will explore design trade-offs…
Added 4 days ago
SOC Design Verification Engineer
Apple
Irvine, CA · San Diego, CA · Sunnyvale, CA
…development, with a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level. It is driven by a world-class,…
Added 4 days ago
SOC Design Verification Engineer
Apple
Irvine, CA · San Diego, CA · Sunnyvale, CA · Waltham, MA
…development, with a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level. It is driven by a world-class,…
Added 4 days ago
Formal Verification Engineer - New College Grad 2027
NVIDIA USA
CA
As a Formal Verification Engineer at NVIDIA, you will work in the formal verification team for the industry's leading chips. We are looking for outstanding candidates with knowledge of…
Added 4 days ago
RTL Design Engineer
Advanced Micro Devices, Inc
Austin, TX
We are seeking a highly motivated RTL IP Design Engineer to join AMD's Security IP (SECIP) Design team. The team is responsible for the architecture, design, and verification of a broad…
Added 4 days ago
Chip Lead
Advanced Micro Devices, Inc
Santa Clara, CA
…while developing broad technical fluency across architecture, design, validation, and production. This role is ideal for an experienced engineer who enjoys solving complex problems, working…
Added 4 days ago
CPU SoC Verification Engineer
Google
San Diego, CA · Mountain View, CA
As a CPU SoC DV Engineer, you will be responsible for ensuring the functional integrity of CPU subsystems from initial RTL simulation through to final silicon characterization. You will…
Added 4 days ago
Wireless SOC Design Verification Engineer
Apple
Irvine, CA · San Diego, CA · Sunnyvale, CA
…new iPhone. You’ll work across the Power Management Unit, the CPU subsystem, on-chip debug infrastructure, PCIe, bus fabric, boot and secure-boot sequencing, and peripherals like SPI and…
Added 4 days ago
Wireless SOC Design Verification Engineer
Apple
Irvine, CA · San Diego, CA · Sunnyvale, CA
Pair with design early - shape the verification plan before RTL lands, not after.
Added 4 days ago
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Senior CAD Software Engineer
Microsoft
CA · NC · OR · Mountain View, CA · Raleigh, NC · Hillsboro, OR · Mountain View · Raleigh · Hillsboro
- $119,800 to $261,000 USD / year
The Microsoft Silicon Engineering and Solutions Team is seeking a passionate and driven software engineer to be a technical leader for our central software team. This team drives…
Added 5 days ago
CPU Design Verification Engineer
Advanced Micro Devices, Inc
Santa Clara, CA
This role focuses on the design verification of next-generation CPUs, translating new CPU features and microarchitectural designs into effective verification plans. The engineer will…
Added 5 days ago
TI
ASIC RTL/SoC Design Engineer
TETRAMEM INC
San Jose, CA
- $110,000 to $300,000 USD / year
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs
Added 8 days ago
FPGA Hardware Engineer
Cisco Systems, Inc.
Milpitas, CA · San Francisco, CA
…boards. You will interface with Diagnostics, Software, Board design, Manufacturing and Hardware Qualification teams to ensure smooth delivery of the project. You are an experienced FPGA…

Intel

Mid-level Physical Design Engineer CPU

Hillsboro, OR, United States

$122,440 to $232,190 USD / year

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Job details

Pay: $122,440 to $232,190 USD / year
Posting language: English
Posted: Sep 30, 2026

Original job description

Job Details:

Job Description:

About the Role

Join a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Mid-level Physical Design Engineer CPU, you will contribute to delivering high-performance, power-efficient silicon using advanced process technologies.

In this role, you will take on increasing ownership within the RTL-to-GDS flow, working on block-level implementation while collaborating closely with cross-functional teams. This position offers strong growth opportunities as you build depth in physical design and SoC development.

What You’ll Do

Key responsibilities will include but not limited to:

Execute physical design implementation for CPU core blocks or subsystems
Perform synthesis, floor planning, place and route (PnR), and design closure activities
Conduct static timing analysis (STA), power analysis, and physical verification
Identify and debug timing, power, and design rule violations
Contribute to achieving timing, power, and area (PPA) targets
Develop and maintain scripts for design automation (e.g., TCL, Python)
Collaborate with RTL design, verification, clocking, and full-chip teams
Support improvements to design flows, methodologies, and best practices
Document technical work and share knowledge within the team

Behavioral traits that we are looking for:

Strong analytical and problem-solving skills
Takes ownership of assigned tasks and delivers with accountability
Works effectively in collaborative, cross-functional environments
Communicates technical information clearly and concisely
Shows adaptability in a fast-paced, evolving engineering environment
Demonstrates continuous learning and skill development

Why Join Us

Work on cutting-edge CPU core designs that power client, server, IoT, and AI platforms used worldwide
Be part of a team driving innovation at advanced semiconductor process nodes
Contribute across the full RTL-to-GDS flow, gaining exposure to complex, high-impact silicon design
Collaborate with experienced engineers across architecture, design, and full-chip integration
Grow your technical expertise through challenging problems, modern tools, and continuous learning opportunities
Join a culture that values inclusion, collaboration, and diverse perspectives while delivering industry-leading technology
Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life.
See Intel Benefits (https://www.intel.com/content/www/us/en/jobs/benefits.html) for more details.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Note:

For information on Intel’s immigration sponsorship guidelines, please see

Intel U.S. Immigration Sponsorship Information (https://www.intel.com/content/www/us/en/jobs/hiring.html)

Minimum Qualifications and Experience :

Bachelors in Computer / Electrical Engineering or related field with 5+ years of relevant work experience. Or a Masters in the same field with 3+ years of relevant work experience.

Your experience described above must be in the following:

Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure
PV convergence (including static timing and power analysis)
Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks
Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby)
Experience with one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP

Preferred Qualifications and Experience :

Industry experience/exposure with CPU Micro-Architecture
Physical design best known practices concerning floor-planning, routing techniques, clock distribution
Static Timing Analysis, Noise analysis, and reliability verification techniques
RTL to GDS methodologies and formal equivalence
Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus)

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Oregon, Hillsboro

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003) .

Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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More about this job

Skills

RTL
GDS
Place-and-route
Python
Problem solving
Adaptability
Electrical engineering
Perl
Ruby

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