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UAM Everfox Tool Engineer - Mid-level
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Job Title: UAM Everfox Tool Engineer - Mid-level
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UAM Everfox Tool Engineer - Senior Level
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Intel Corporation

EDA Tools Software Engineer

AZ, United States
CA, United States

$128,880 to $245,160 USD / year

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Job details

Pay: $128,880 to $245,160 USD / year
Experience: Bachelors & 4+ years or Masters & 3+ years in Electrical Engineering, Computer Engineering, or a related field of related experience in the following.
Posting language: English
Posted: Nov 4, 2026

Original job description

Job Details:

Job Description:

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone.

We are looking for an experienced engineer to join the PDK Reliability Verification / EMIR team. This role will contribute to the development, qualification, and delivery of production-quality EM/IR reliability collateral and methodologies across advanced process technologies. The team owns PDK and related EMIR enablement and supports multiple EDA platforms including Synopsys Totem/Totem-SC and PrimeSim-EMIR, Cadence Voltus/Voltus-XFi, and Ansys RedHawk-SC. The work includes Custom and ASIC EMIR, advanced process enablement, 3DIC-related reliability verification, and thermal enablement.

Responsibilities

Develop, qualify, and maintain PDK EMIR collateral, documentation, and technology-specific configurations. Own or contribute to PDK and Reliability Technology Kit ( RTK ) development, qualification, QA, and release readiness. Develop and maintain test structures and automated validation for EM/IR collateral, including validation and cross-tool correlation. Enable new process features and advanced interconnect structures across current and future process technologies. Debug complex modeling and correlation issues involving extraction, EM/IR analysis, PDK collateral, and EDA tools, working from root cause through validated resolution. Perform cross-tool/vendor correlation across supported EMIR platforms and drive issues to closure with EDA vendors. Work closely with PDK, Extraction, LVS, QnR, ASIC RV, design-flow, and customer-facing teams. Support adoption and qualification of next-generation solutions such as Totem-SC and emerging EMIR/extraction capabilities. Improve development and QA efficiency through Python/Tcl/Perl/Skill or similar automation, data analysis, regression infrastructure, and AI-assisted development and debug where appropriate. Partner with Synopsys, Cadence and internal engineering teams to resolve tool limitations, qualify new releases, and ensure production readiness.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.

Minimum Qualifications:

Bachelors & 4+ years or Masters & 3+ years in Electrical Engineering, Computer Engineering, or a related field of related experience in the following.

Strong semiconductor design, EDA, physical-design, PDK, or reliability-verification background.

Experience in one or more of:

Electro Migration/IR or reliability verification Parasitic extraction SPICE/post-layout simulation PDK/technology-file development Physical verification EDA tool qualification Strong scripting/automation skills, preferably Python, Tcl, Perl, Skill or equivalent. Strong debugging skills with the ability to isolate problems spanning technology collateral, extraction, simulation, and analysis. Ability to work effectively across multiple engineering organizations and with EDA vendors.

Preferred Qualifications:

Experience with Totem/Totem-SC, PrimeSim-EMIR, Voltus/Voltus-XFi, RedHawk-SC, StarRC, Quantus/QRC, or similar tools. Understanding of Electromigration, IR drop, current-density limits, via/metal reliability, resistance modeling, and advanced interconnect structures. Experience developing automated test structures, regression environments, correlation methodologies, or production PDK QA. Understanding of advanced-node PDK development and release processes. Experience taking ambiguous technical problems from initial investigation through implementation, validation, documentation, and production release.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Arizona, Phoenix

Additional Locations:

US, California, Folsom, US, California, Santa Clara

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $128,880.00-245,160.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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