Sr RTL IC Design Engineer

Required Skills & Experience

• Bachelors degree (in Electrical Engineering, Electronics Engineering, Computer Science, Computer Engineering)
• 12-15 years experience of RTL/digital design
• Strong experience with Verilog/SystemVerilog coding for RTL
• Strong RTL debugging skills
• Understanding of Clock Domain Crossing and Reset Domain Crossing
• Strong written and verbal communication

Nice to Have Skills & Experience

• Semiconductor industry experience
• PCIe protocol
• CXL protocol
• AMBA protocols
• RAID Storage designs
• PCIe Switch designs

Job Description

Insight Global is looking for three Senior level IC Design Engineers to join a leading semiconductor company sitting out of Colorado Springs, Colorado or San Jose, California. This position involves working with the latest technology to continue driving next generation AI/ML ecosystems through their PCIe Switch Products – and managing mega datacenters, while leading world class performance, through their Enterprise Storage Products. More specifically, this position will require in-depth knowledge surrounding all aspects of implementation and supporting RTL designs using Verilog/SystemVerilog. This will be a fully onsite position, with regular hours Monday - Friday.

Responsibilities include:

• High-level architecture specification analysis – interactive authoring and review.
• Micro-architecture development and documentation.
• High-quality, high-performance Verilog/SystemVerilog RTL implementation based on a design specification – may also include areas such as asynchronous clock domain crossings, multiple power domains, low-power design, complex algorithms, deep computations and pipelining, multi-threaded designs, and integrating third-party IP.
• Converging the design to timing closure by RTL optimization strategies.
• Superb RTL debugging skills with well thought out robust RTL solutions.
• Working with cross functional teams such as Verification Engineering, Software/Firmware Engineering, Emulation Engineering, and Validation Engineering to support any issues that may arise on the RTL design.
• Lab support for silicon as it progresses through validation.

This position can range between $127-$203K depending on experience, including a 20%+ yearly bonus, RSUs granted upon signing, 401k including company matching, competitive benefits package, as well as company paid holidays, paid sick leave and vacation time. This position also provides full relocation.