IC Verification Engineer

Required Skills & Experience

10+ years of ASIC, SoC, core, or block-level design verification experience

Expert-level SystemVerilog and UVM

Experience architecting scalable, reusable UVM testbench environments

Strong verification planning, constrained-random testing, and functional coverage experience

Proven regression debugging, waveform analysis, and coverage-closure skills

Experience completing at least one full ASIC cycle from architecture through tapeout

Ability to independently lead verification for a core or major functional block

Strong teamwork, communication, coachability, and knowledge-sharing skills

Nice to Have Skills & Experience

PCIe or another complex, multilayer protocol

Physical-layer or PHY verification experience

Job Description

A client of Insight Global is seeking senior IC Verification Engineers with deep, hands-on expertise in SystemVerilog and UVM. Candidates must have owned the verification lifecycle, including testbench architecture, test planning, functional coverage, regression debugging, hardware debug, and verification closure.

Responsibilities:

Architect scalable and reusable SystemVerilog/UVM testbenches

Develop verification strategies and test plans for block, core, and SoC features

Build constrained-random and pseudo-random tests

Develop functional coverage and drive verification to closure

Debug regression failures and address coverage gaps

Support hardware debug and full ASIC-cycle execution

Document verification environments, tests, and strategies

Collaborate with design and architecture teams