ASIC Verification Engineer

Required Skills & Experience

Bachelor's degree in Electrical Engineering or a related field. UVM Based testbench development. Experience in ASIC or SOC verification. Demonstrated experience in developing test plans and verification infrastructure. Practical knowledge of verification methodologies from block level to system level. C coding for firmware delivery for post silicon bringup

Nice to Have Skills & Experience

Experience with formal verification techniques including abstraction and end-to-end checking. Experience with industry-standard tools and scripting languages (Python or Perl) for automation. System Verilog coding and debug. AI based CAD efficiency improvisation initiatives High speed serial protocols preferred UCIe, PCIE etc Analog debug experience including DAC/ADC & calibrations white-box verification.

Job Description

Join our innovative team developing next-generation silicon solutions for Cisco's silicon one group.

We are seeking a collaborative Design Verification Engineer with 5-12 years of industry experience to help create cutting edge System-on-Chip (SoC) designs delivered first time right. You will work in a collaborative environment, participating in architectural decisions and verification strategies that directly impact product success. This team values diverse perspectives and creative problem-solving approaches to deliver exceptional customer experiences.

What You'll Do:

Develop and implement Universal Verification Methodology (UVM) based verification environments. Create comprehensive verification plans at both block and system levels. Design and implement verification components including assertions, traffic generators, agents, and scoreboards. Collaborate with cross-functional teams to evaluate design testability and verification requirements. Lead debug efforts and provide solutions for complex technical challenges.