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Senior Software Engineer
McLean, VA
Ability to analyze system architecture and contribute to design planning.
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SharePoint Engineer / Portal Administrator
JANUS Research Group
Fort Bliss, TX
Candidates must have an active Secret clearance and verify, before applying, that you meet the minimum requirements of the position
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Houston, TX
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Propulsion Engineer (Raptor Integration)
SpaceX
Starbase, TX · Brownsville, TX
…time they fly. Today, the team is focused on enabling rapid design iteration by taking lessons from flight and engine testing and applying those lessons across the fleet. In the future, the…
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Applications Engineer II-MMIC
Mini-Circuits
Melville, NY
The Applications Engineer II position is a critical part of the technical support that Mini-Circuits provides. The individual in this role will have the opportunity to work with peers to…
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Senior Manager, Agentic AI Engineer
PWC US
IL-Chicago, IL · NC-Raleigh, NC · NC-Charlotte, NC · OH-Cincinnati, OH · OH-Cleveland, OH · SC-Columbia, SC · OH-Columbus, OH · TX-Dallas, TX · VA-Richmond, VA · MD-Baltimore, MD · NY-Rochester, NY · IL-Rosemont, IL · CA-Sacramento, CA · MA-Boston, MA · MO-St. Louis, MO · UT-Salt Lake City, UT · TX-San Antonio, TX · CA-San Diego, CA · CA-San Francisco, CA · CA-Silicon Valley, CA · WA-Seattle, WA · SC-Spartanburg, SC · NY-Albany, NY · CT-Stamford, CT · FL-Tampa, FL · GA-Atlanta, GA · OH-Toledo, OH · OK-Tulsa, OK · TX-Austin, TX · DC-Washington, DC · CO-Denver, CO · IA-Des Moines, IA · FL-Boca Raton, FL · MI-Detroit, MI · NY-Buffalo, NY · NJ-Florham Park, NJ · TX-Fort Worth, TX · NC-Greensboro, NC · CT-Hartford, CT · TX-Houston, TX · IN-Indianapolis, IN · MI-Grand Rapids, MI · CA-Irvine, CA · FL-Jacksonville, FL · MO-Kansas City, MO · NV-Las Vegas, NV · AR-Little Rock, AR · CA-Los Angeles, CA · KY-Louisville, KY · AL-Birmingham, AL · AR-Fayetteville, AR · NY-Melville, NY · FL-Miami, FL · WI-Milwaukee, WI · MN-Minneapolis, MN · VT-Montpelier, VT · TN-Nashville, TN · LA-New Orleans, LA · NY-New York, NY · OK-Oklahoma City, OK · FL-Orlando, FL · PA-Philadelphia, PA · AZ-Phoenix, AZ · PA-Pittsburgh, PA · OR-Portland, OR
What You Must Have
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Applications Engineer II-MMIC
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The Applications Engineer II position is a critical part of the technical support that Mini-Circuits provides. The individual in this role will have the opportunity to work with peers to…
Added 8 mins ago
Transportation Engineer Specialist
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Frankfort, KY
Must have four years of engineering experience in addition to that required for licensure as a Professional Engineer · Must possess a valid driver's license prior to employment in this job classification

Google

SoC DFT Engineer, Cloud

Sunnyvale, CA, United States

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Job details

Experience: 5 years of experience in DFT architecture, implementation, and verification for SoCs.
Posting language: English

Original job description

In most instances, this position requires in-person interviews as part of the hiring process.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience in DFT architecture, implementation, and verification for SoCs.
Experience in silicon bring-up, debug, or validation of DFT features.
Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT).

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
10 years of experience in DFT architecture, implementation, and verification for SoCs.
Experience with various fault models (e.g., Stuck-at, Transition, Cell-Aware, Path Delay, etc.).
Experience in DFT flow, including architecture, IP integration (e.g., Test controllers, TAP, MBIST), and interaction with synthesis and verification flows.
Experience with industry-leading EDA tools for DFT, such as Synopsys (e.g., Design Compiler, DFT Max) or Siemens EDA (e.g., Tessent, TestKompress).
Knowledge of test standards (e.g., IEEE 1149.1, 1687) and test data Formats (e.g., BSDL, STIL).

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a DFT Engineer, you will be responsible for defining, implementing and deploying advanced design-for-test (DFT) methodologies including Scan, MBIST, JTAG and iJTAG, for highly digital or mixed-signal chips or IPs. You will define silicon test strategies, DFT/DFD architecture, and create DFT and Debug specifications for next generation SoCs. In partnership with the Silicon Engineering team, you will also be responsible for diagnosing memory and logic failures, increasing production quality, and enhancing yield and reducing test cost. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, MBIST, ATPG and I/JTAG, and associated boot up and execution sequences.
Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high test quality.
Develop diagnostic databases, software and hardware for logic and memory fail debug.
Design and implement system level test strategy.
Implement core DFT circuitry, including insertion and hook-up of scan chains, DFT compression, Logic BIST, TAP controllers, and Memory BIST (MBIST) logic for IP blocks.

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Jobs in the United States