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Lead Director - Security Operations Center (SOC)
CVS Health
Honolulu, HI
As the leader of the SOC function, this role is accountable for building and maturing security operations capabilities that balance security, scalability, and business agility. The Lead…
Added 2 mins ago
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Senior Hardware Quality Engineer
Microsoft
WA · TX · NC · CA · OR · Redmond, WA · Austin, TX · Raleigh, NC · Mountain View, CA · Hillsboro, OR · Redmond · Austin · Raleigh · Mountain View · Hillsboro
- $119,800 to $261,000 USD / year
…enablement. The position partners closely with data center operations, firmware, platform engineering, diagnostics, and vendor teams to improve hardware reliability, reduce repeat…
Added 2 mins ago
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Principal Software Engineer, AI Infra Management and Ops
Microsoft
United States
- $142,800 to $274,800 USD / year
As a Principal Software Engineer, you will lead the design and evolution of cloud-native platforms, distributed systems, and infrastructure services that support service lifecycle…
Added 2 mins ago
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Principal Design Verification Engineer (Design or DV)
Microsoft
CA · WA · NC · Mountain View, CA · Redmond, WA · Raleigh, NC · Mountain View · Redmond · Raleigh
- $142,800 to $304,200 USD / year
Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200…
Added 2 mins ago
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Principal Hardware Engineer
Microsoft
WA · CA · OR · TX · NC · Redmond, WA · Mountain View, CA · Hillsboro, OR · Austin, TX · Raleigh, NC · Redmond · Mountain View · Hillsboro · Austin · Raleigh
- $142,800 to $304,200 USD / year
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Added 5 mins ago
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WA · Redmond, WA · Redmond
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Senior Platform Systems Engineer
Microsoft
WA · CA · OR · TX · Redmond, WA · Mountain View, CA · Hillsboro, OR · Austin, TX · Redmond · Mountain View · Hillsboro · Austin
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RTL Design Engineer, Google
Google
Sunnyvale, CA
As a RTL Design Engineer, you will join a team working on SoC-level RTL design for our data center accelerators. You will design RTL IP with the focus on chassis infrastructure, including…
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Google

RTL Design Engineer, Google

Sunnyvale, CA, United States

Apply on google.com About employer

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Job details

Posting language: English

Original job description

In most instances, this position requires in-person interviews as part of the hiring process.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
Experience in SystemVerilog for creating microarchitecture specifications and synthesizable RTL.
Experience using Python, Tcl, or Perl for automating design tasks and data analysis.
Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.
Experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
2 years of experience with high-performance ASIC design in Phase-Locked Loop, Frequency-Locked Loop, and Delay-Locked Loop integration.
Experience implementing clock skipping, dynamic voltage and frequency scaling (DVFS), and fine-grained clock gating for low-power SoC optimization.
Experience utilizing AI productivity tools to streamline individual, business or development workflows.
Proficiency in Python or Perl for automating design scripts and analyzing clock-tree data.
Understanding of clock distribution challenges, including jitter, skew management, and duty-cycle distortion.

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a RTL Design Engineer, you will join a team working on SoC-level RTL design for our data center accelerators. You will design RTL IP with the focus on chassis infrastructure, including fabric bridges and sensor telemetry network, also participate in developing infrastructure and methodology that form the foundation of our SoCs (i.e., error handling, debug, chip management and SOC chassis, etc.). You will build a global understanding of how our accelerators are built from concept to production. This is a highly cross-functional role that will require you to coordinate and co-design with our software and system hardware counterparts. In this role, you will utilize a background in RTL design and lead to multi-faceted efforts involving many stakeholders. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $116000 - $165000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Create and review clock control subsystem's design micro-architecture specifications.
Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
Work with architecture and power teams to evaluate features and their impact.
Work with Design Validation (DV) teams to create test plans to verify and debug design RTL.
Work with physical design teams to ensure design meets physical requirements and timing closure.

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More about this job

Skills

RTL
Electrical engineering
Computer engineering
Computer science
SystemVerilog
Python
Perl
Data analysis
EDA
ML
Work as a team
Google Cloud
Research

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Work requirements

Jobs in the United States