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Added 5 hours ago
M
Principal Design Engineer
Microsoft
NC · CA · Raleigh, NC · Mountain View, CA · Raleigh · Mountain View
- $142,800 to $304,200 USD / year
We are looking for a Principal Design Engineer to join the team.
Added 1 day ago
DFT Lead Engineer
LSI Corporation
United States
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Products Division)’s designs – DFT Architecture, Test insertion and…
Added 1 day ago
ASIC Physical Design, Principal Engineer
Synopsys
Sunnyvale, CA
You can explain a complex physical design tradeoff to an analog engineer, a front-end architect, and a customer program manager, and have all three understand what matters to them
Added 1 day ago
CU
Principal Application Engineer
CADENCE US
United States
- $127,400 to $236,600 USD / year
We are looking for a Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital Implementation and Signoff tools. The candidate will…
Added 2 days ago
Principal ASIC Engineer
Echodyne Corp
Kirkland, WA
Echodyne is seeking a Principal ASIC Engineer to join our fast-growing team.
Added 2 days ago
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Dsp Engineer
Actalent
Irvine, CA
- $100,000 to $200,000 USD / year
Job Title: DSP EngineerJob DescriptionWe are seeking an experienced DSP Engineer to define communication system architectures and develop advanced digital signal processing algorithms for…
Added 2 days ago
Principal Firmware Engineer - Digital ASIC
Blue Origin LLC
Seattle, WA
You will work closely with ASIC design, verification, hardware, communications systems, test, and manufacturing engineering teams to ensure successful firmware integration and delivery…
Added 2 days ago
SOC Engineering, Principal Engineer
Synopsys
Austin, TX
15+ years of ASIC/SoC design verification experience, including hands-on subsystem or full-chip ownership through multiple tape-outs.
Added 3 days ago
Senior Principal Engineer-DFT
MSI - (Marvell Semiconductor Inc.) US
Santa Clara, CA
The execution involves Design-for-Test Architecture definition, Implementation of various DFT/DFX features, Validation , IP-DFT, STA, pattern generation & Post-Silicon Bringup and Debug for…
Added 3 days ago
Senior Lead Design Engineer - RTL Design
Altera Corporation
San Jose, CA
Altera is seeking a Senior Lead Design Engineer - RTL Design to provide hands-on technical leadership for the RTL architecture, design, integration, and delivery of next-generation FPGA and…
Added 4 days ago
Principal ASIC Design Engineer / Chip Architect
Chelsea Search Group
Remote, United States
…through silicon. This is a highly hands-on opportunity for an engineer who enjoys solving challenging digital design problems and working across the full ASIC/SoC development flow. You’ll…
Added 4 days ago
Principal ASIC Design Engineer – Chip Architecture & RTL
Chelsea Search Group
Remote, United States
…through silicon. This is a highly hands-on opportunity for an engineer who enjoys solving challenging digital design problems and working across the full ASIC/SoC development flow. You’ll…
Added 4 days ago
Principal Engineer, Physical Design (ASIC Place & Route) (San Jose, CA) (7429)
TSMC
San Jose, CA
As a Principal Physical Design Engineer, you will serve as a foundational pillar in translating complex architectural concepts into high-yield, production-ready silicon. Operating at the…
Added 4 days ago
DFT Lead Engineer
LSI Corporation
United States
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Products Division)’s designs – DFT Architecture, Test insertion and…
Added 4 days ago
Senior Mechanical Engineer
Hewlett Packard Enterprise
Sunnyvale, CA
Reporting to the Head of Mechanical Engineering, the Senior Mechanical Engineer will be a hands-on individual contributor responsible for the mechanical design, structural analysis,…
Added 4 days ago
Principal Mechanical Engineer
Hewlett Packard Enterprise
Sunnyvale, CA
Reporting to the Head of Mechanical Engineering, the Principal Mechanical Engineer will be a hands-on individual contributor responsible for the mechanical design, structural analysis,…
Added 4 days ago
Principal PCS/PMA RTL Design Engineer
Astera Labs
San Jose, CA · CA
Astera Labs is seeking a Principal PCS/PMA RTL Design Engineer to join our San Jose design team, focused on the Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) logic for…
Added 5 days ago
Senior/Principal Physical Design Engineer (remote)
Chelsea Search Group
Remote, United States
We are seeking an experienced Physical Design / P&R Engineer to take a key role in delivering complex, high-performance ASICs from RTL/netlist through GDSII and tapeout. You’ll own critical…
Added 5 days ago
Principal Design Verification Engineer (Silicon Engineering)
SpaceX
Redmond, WA
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation,…
Added 5 days ago
Principal/Sr. Principal FPGA Engineer
Northrop Grumman
Rolling Meadows
As a Principal / Sr. Principal FPGA Design Engineer, you will join a diverse, high-performing team responsible for the end-to-end development of advanced RF and EO/IR products. You will…
Added 5 days ago
Principal/Sr. Principal FPGA Engineer
CORP-Corporate Office
United States
As a Principal / Sr. Principal FPGA Design Engineer, you will join a diverse, high-performing team responsible for the end-to-end development of advanced RF and EO/IR products. You will…
Added 5 days ago
SoC Principal Physical Design Engineer
Synopsys
Austin, TX
10 to 15+ years of hands-on ASIC or SoC physical design experience with a proven track record of multiple successful tapeouts at advanced process nodes
Added 5 days ago
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Principal Digital IC Design Engineer
Skyworks
Richardson
- $122,900 to $255,200 USD / year
We are seeking a experienced and visionary Principal ASIC Engineer to lead our next-generation silicon development. In this high-impact technical leadership role, you will own the full-flow…
Added 6 days ago
Principal Engineer, Project Management - Chip Power
NVIDIA Corporation
North District, IL
NVIDIA Switches ASIC group is seeking a top-tier ASIC Power technical manager to lead the development of our next-generation ASICs Power execution, modelling, and optimization. Join us in…
Added 7 days ago
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Principal Digital Design Engineer
NAVITAS SEMICONDUCTOR USA, INC.
Torrance, CA
- $170,000 to $190,000 USD / year
We are seeking a Principal Digital Design Engineer to join our fast-growing, collaborative team. The ideal candidate is self-motivated, energetic, and able to thrive in a high-growth,…

Google

Principal Chipset Project Engineer

Mountain View, CA, United States

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Job details

Posting language: English
Posted: Oct 13, 2026

Original job description

Principal Chipset Project Engineer

Share Principal Chipset Project Engineer

corporate_fare Google place Mountain View, CA, USA bar_chart DirectorShare Principal Chipset Project Engineer

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Science, or a related field, or equivalent practical experience.
15 years of experience with custom silicon design, SoC/ASIC implementation, or hardware-software co-design.
10 years of technical leadership experience, including experience directing SoC development programs from concept to mass production.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Science, or a related field.
Experience managing global, cross-functional engineering deliverables and aligning schedules/dependencies across matrixed organizations.
Excellent change-management and operational leadership skills, with experience coordinating teams across global sites.
Expertise in driving complex hardware and software system-level debug and root-cause analysis.
Technical understanding of custom IP integration, physical design flows, and hardware-software co-design principles.

About the job

As the Principal Chipset Project Engineer, you will serve as the primary technical leader for the engineering planning and execution of the Chipset from early product definition stages through launch. This is a cross-functional leadership role that bridges the gap between hardware architecture, IP development, physical implementation, and software readiness. Your primary goal is to deliver an efficient chipset solution for the agentic era on-schedule, within budget, and with Power, Performance, Area, and Cost (PPA-C) metrics.

Int this role, you will drive end-to-end technical execution across a highly matrixed global workforce to ensure custom hardware innovations land seamlessly in production and are optimized for first-party software experiences.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $275000 - $382000 (USD) + 30% bonus target + equity + benefits

Learn more aboutbenefits at Google (https://www.google.com/about/careers/applications/benefits/) .

Responsibilities

Direct the execution of the entire SoC lifecycle, from initial chip definition and top-level architecture through tape-out, silicon bring-up, and final mass production.
Collaborate with Devices and Services Product Group (DSPG) Silicon, Software, and Pixel Hardware teams, ensuring hardware innovations have day-one software sponsorship and land seamlessly in production.
Coordinate deliverables across a highly matrixed global workforce, aligning schedules, managing dependencies, and actively resolving complex technical blockers.
Lead critical debug forums to drive complex system failure signatures to rapid root-cause closure by driving actions across all teams.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google'sApplicant and Candidate Privacy Policy (./privacy-policy) .

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See alsoGoogle's EEO Policy (https://www.google.com/about/careers/applications/eeo/) ,Know your rights: workplace discrimination is illegal (https://careers.google.com/jobs/dist/legal/EEOC_KnowYourRights_10_20.pdf) ,Belonging at Google (https://about.google/belonging/) , andHow we hire (https://careers.google.com/how-we-hire/) .

If you have a need that requires accommodation, please let us know by completing ourAccommodations for Applicants form (https://goo.gl/forms/aBt6Pu71i1kzpLHe2) .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.

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Skills

Electrical engineering
Computer science
Leadership
Change management
Root cause analysis
Design principles
Microsoft Teams
Research
Recruitment

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