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Business Development Representative
Swarmia
New York, NY
- $110,000 to $140,000 USD / year
This is a high-ownership role. You will design and run multi-channel sequences, experiment with messaging and channels, and help shape how we sell to technical buyers.
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Data Scientist III - Spot Pricing
Uber Freight
Chicago, IL
- $99,000 to $151,000 USD / year
We are seeking an exceptionally passionate person to join our Marketplace Data Science team. As a Data Scientist focused on Spot Pricing, you will be driving the evaluation and development…
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Software Engineer, Growth
Kalshi
New York City, NY
…delivery orchestration, and client-facing notification features. Design, develop, and operate data-driven systems supporting personalization, targeting, ranking, and user engagement for…
Added 1 min ago
Safety Intern
Sargento Foods
Plymouth, WI
Must be able to define problems, collect data, establish facts and draw valid conclusions.
Added 1 min ago
Senior Journey Architect
GitLab
Remote, United States
GitLab is the intelligent orchestration platform for DevSecOps. GitLab enables organizations to increase developer productivity, improve operational efficiency, reduce security and…
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Lead Journey Architect
GitLab
Remote, United States
GitLab is the intelligent orchestration platform for DevSecOps. GitLab enables organizations to increase developer productivity, improve operational efficiency, reduce security and…
Added 1 min ago
Vice President, Cyber Threat, Offensive Security & Incident Response (Hybrid)
Globe Life And Accident Insurance Company
McKinney, TX
…agents, and third-party AI services, covering prompt injection, data leakage, model abuse, insecure agent permissions, and supply-chain risks aligned with frameworks such as OWASP Top 10…
Added 1 min ago
Production Associate Pannel Plating
TTM TECHNOLGIES INC
CHIPPEWA FALLS, WI
…time-to-market, representing how TTM\'s time-critical, one-stop design, engineering and manufacturing services enable customers to reduce the time required to develop new products and bring…
Added 1 min ago
Toolmaker Moldmaker
CIRTEC MEDICAL CORP
STURTEVANT, WI
Added 1 min ago
Finishing Technician
KOCH INDUSTRIES INC
NEW RICHMOND, WI
Added 1 min ago
Design Engineering Intern
PRO ACTIVE ENGINEERING
SUN PRAIRIE, WI
Added 1 min ago
Quality Engineer
KOCH INDUSTRIES INC
HUDSON, WI
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Data Center Sales Executive Power Ge
REHLKO
KOHLER, WI
Added 1 min ago
VP, Global Finance Risk / Prime Services Risk
BMO Capital Markets Corp.
NY
Comfort with using data querying skill set to design risk dashboards, graphic user interfaces linked to internal databases and enhanced risk reporting.
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Design Engineering Intern
PRO ACTIVE ENGINEERING
SUN PRAIRIE, WI
Added 1 min ago
Toolmaker Moldmaker
CIRTEC MEDICAL CORP
STURTEVANT, WI
Added 1 min ago
Programming Analyst
ACE PRECISION
OCONOMOWOC, WI
Added 1 min ago
Quality Engineer
KOCH INDUSTRIES INC
HUDSON, WI
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Vice President of Training & Education
Regis Corporate Career Site
Minneapolis, MN
- $170,000 to $190,000 USD / year
The VP of Training & Education will lead the design and delivery of scalable, innovative learning solutions that enhance operational excellence, elevate service quality, and drive…
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Hair Stylist - Licensed Cosmetologist
Regis Corporate Career Site
ROSENBERG, TX
- Up to $40 USD / hour
Unlimited career advancement instructor opportunities-includes domestic trips for our design artistic team
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RC
Hair Stylist - Licensed Cosmetologist
Regis Corporate Career Site
PEARLAND, TX
- Up to $40 USD / hour
Unlimited career advancement instructor opportunities-includes domestic trips for our design artistic team
Added 1 min ago
RC
Hair Stylist - Licensed Cosmetologist
Regis Corporate Career Site
KINGWOOD, TX
- Up to $40 USD / hour
Unlimited career advancement instructor opportunities-includes domestic trips for our design artistic team
Added 1 min ago
RC
Hair Salon Manager or Hair Designer - Licensed Cosmetologist
Regis Corporate Career Site
LAKE JACKSON, TX
- Up to $40 USD / hour
Unlimited career advancement instructor opportunities-includes domestic trips for our design artistic team
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Eikon - Radar Firmware Engineer
Eikon Research Inc
Huntsville, AL
- $130,000 to $165,000 USD / year
…well-documented, correct code/designs. A strong understanding of digital design fundamentals, firmware development processing, and parallel processing paradigms is…
Added 1 min ago
Software Dev Engineer I, Security Platform
Twitch Interactive, Inc.
Seattle, WA · Irvine, CA · San Francisco, CA
- Experience working with large-scale event or log data, including event-driven architectures, asynchronous processing, or batch/streaming pipelines.

Google

Physical Design Technical Lead, ASIC, TPU

Sunnyvale, CA, United States

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Job details

Posting language: English

Original job description

In most instances, this position requires in-person interviews as part of the hiring process.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in physical design, including leading full-chip or sub-chip implementation such as RTL2GDSII and overseeing key stages like floorplanning, place and route, and timing closure for high-speed ASICs across various process nodes.
Experience in Python, Tcl, or Perl scripting.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with Cadence Innovus, Synopsys DP, Mentor Calibre, and StarRC, plus understanding of foundry technology files, rule decks, physical sign-off, and 2.5D/3D packaging.
Technical leadership experience managing execution schedules, mitigating risks, and driving cross-functional collaboration with internal teams and external vendors.
Understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
Ability to navigate ambiguity, scale leadership across the physical design hierarchy, and excellent communication skills to articulate complex technical challenges to stakeholders.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google’s Tensor Processing Units (TPUs) are incredibly complex, pushing the boundaries of physical design, power, and performance. In this role, you will provide technical leadership for the physical design of our next-generation AI silicon. Because of the sheer scale of our chips, our physical design leadership is highly dynamic; you will be expected to drive end-to-end execution with a scope that scales from owning highly complex, critical macro-subsystems up to overarching project-wide top-level implementation, depending on project needs. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits

Learn more about benefits at Google.

Lead the physical design implementation and strategy for high-performance silicon, with leadership scope ranging from critical, high-complexity subchips to overarching top-level execution based on project phases and team needs.
Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.

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