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Added 5 mins ago
HP
Inside Sales Associate
High Point Networks LLC
West Fargo, ND · Billings, MT · Pueblo, CO · Sioux Falls, SD
- $55,000 to $65,000 USD / year
High Point Networks is a leading provider of information technology solutions in both SMB and enterprise-level markets, servicing customers from coast to coast. We specialize in anything…
Added 7 mins ago
Journeyman MBSE Systems Engineer
Sabre Systems LLC
Patuxent River, MD
Sabre Systems is currently recruiting a Journeyman MBSE Systems Engineer for the Model-Based Systems Engineering Division to support the V-22 Joint Program Office (PMA-275) at Patuxent…
Added 7 mins ago
Senior MBSE Systems Engineer
Sabre Systems LLC
Patuxent River, MD
Sabre Systems is currently recruiting a Senior MBSE Systems Engineer for the Model-Based Systems Engineering Division to support the Heavy Lift Helicopter Program Office (PMA-261) at…
Added 7 mins ago
Senior MBSE Systems Engineer
Sabre Systems LLC
Patuxent River, MD
Sabre Systems is currently recruiting a Senior MBSE Systems Engineer for the Model-Based Systems Engineering Division to support the V-22 Joint Program Office (PMA-275) at Patuxent River…
Added 7 mins ago
Journeyman MBSE Systems Engineer
Sabre Systems LLC
Patuxent River, MD
Sabre Systems is currently recruiting a Journeyman MBSE Systems Engineer for the Model-Based Systems Engineering Division to support the V-22 Joint Program Office (PMA-275) at Patuxent…
Added 7 mins ago
Journeyman MBSE Systems Engineer
Sabre Systems LLC
Patuxent River, MD
Sabre Systems is currently recruiting a Journeyman MBSE Systems Engineer for the Model-Based Systems Engineering Division to support the PMA-228 at Patuxent River Naval Air Station in…
Added 7 mins ago
Manufacturing & Quality Engineer (Journeyman)
Sabre Systems LLC
Patuxent River, MD
Sabre Systems is currently recruiting a Journeyman Manufacturing & Quality Engineer for the Manufacturing and Quality Engineering (M&QE) Division, in NAVAIR’s Systems Acquisition Group. The…
Added 7 mins ago
Senior MBSE Systems Engineer
Sabre Systems LLC
Patuxent River, MD
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Added 7 mins ago
G
Traffic Engineer
GPAC
Chicago, IL
- $95,000 to $135,000 USD / year
As a Traffic Engineer, you'll play a pivotal role in designing, analyzing, and optimizing traffic flow for the future. You'll collaborate with a team of brilliant minds, utilizing your…
Added 8 mins ago
Civil Engineer - Land Development
GPAC
Savannah, GA
We are seeking a Civil Design Engineer with experience in land development to support a variety of residential, commercial, and mixed-use projects. In this role, you'll contribute to…
Added 8 mins ago
Civil Engineer - Land Development
GPAC
Harrisburg, PA
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Added 8 mins ago
Civil Engineer - Land Development
GPAC
York, PA
We are seeking a Civil Design Engineer with experience in land development to support a variety of residential, commercial, and mixed-use projects. In this role, you'll contribute to…
Added 8 mins ago
Senior AI Engineer, Banking Technology
Citibank, N.A.
United States
Citi’s Banking Technology organization is seeking a highly hands-on Senior AI Engineer to design, build, and deploy cutting‑edge AI solutions for Investment, Corporate, and Commercial…
Added 9 mins ago
Civil Structural Engineer
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Dallas, TX
…mentorship, innovation, and delivering high-quality structural…
Added 9 mins ago
Civil Structural Engineer
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Added 9 mins ago
Transportation Engineer
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Civil Roadway/Transportation Design Engineer with responsible for the planning, design, and development of transportation and roadway infrastructure projects from preliminary concepts…
Added 10 mins ago
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Cost Engineer
Aston Carter
Costa Mesa, CA
- $75 to $85 USD / hour
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SIOP Manager - Pneumatics Platform
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Added 11 mins ago
Principal/Senior Principal Systems Engineer (AHT)
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Added 11 mins ago
Manager Information Technology 3
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…in delivering intelligence, surveillance, and reconnaissance solutions for classified and unclassified missions in space. As part of Eastern Region Systems Engineering, Integration and Test…
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Google

Package Design Engineer

Sunnyvale, CA, United States

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Job details

Experience: 8 years of experience in chip package substrate design using Cadence APD or Mentor Expedition.
Posting language: English

Original job description

In most instances, this position requires in-person interviews as part of the hiring process.

Minimum qualifications:

Bachelor's degree in Mechanical Engineering, Material Engineering, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience.
8 years of experience in chip package substrate design using Cadence APD or Mentor Expedition.
Experience in chip package substrate layout, design verification, DFM and taping out for production.
Experience in design automation and scripting.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Experience in working with cross-functional teams including chip design, SI/PI, and PCB design teams.
Experience in 2.5D/3.5D advanced package design.
Experience in physical verification flow (LVS, DRC, connectivity).
Experience with CAD for creating simple mechanical drawings, such as package outline drawings (POD).
Ability to write scripts to customize elements of the Cadence or Mentor workflow.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Chip Package Designer on the Silicon Integration team, your role is to develop package substrate designs of advanced (2.5D/3.5D) packaging technologies for ML chips. This involves collaborating with SI/PI, Thermal/Mechanical, Assembly, and PCB engineers to create complex, high-performance substrate designs, where your goal is to optimize package substrate design for electrical performance, reliability, and assembly. You will manage all phases of the design process, including routing feasibility, test vehicle creation, product designs, conducting design reviews, artwork export, DFM process and generating final documentation. Additionally, you will be instrumental in identifying and incorporating advanced chip packaging technologies into the Google chip product design pipeline, which contributes to successful chip deployment in data centers, ensuring the best optimized PPA (Power, Performance, Area) designs and enhancing system performance relative to TCO (Total Cost of Ownership) and power. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Develop physical package substrate design of large form-factor package for ML high-performance computers (HPCs).
Develop and implement the methodology and CAD flow for efficient substrate design and enhanced productivity.
Manage and drive co-design initiatives across chip, package, and system levels, including securing production sign-off for package designs.
Collaborate closely with signal integrity/power integrity (SI/PI), thermal, and mechanical engineering teams to refine and optimize product package designs, test vehicles, and mock-up designs for product feasibility.
Define and document the requirements for the package substrate design and bill of materials (BOM).

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More about this job

Skills

Mechanical engineering
Electrical engineering
Computer engineering
Computer science
Printed circuit boards
Technical drawings
POD
Workflow
Design package
Packaging
ML
Assembly
Design process
Documentation
Google Cloud
Research

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