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Added 2 mins ago
CO
Network Engineer - Public Works
City of San Jose
San Jose, CA
- $130,930.8 to $159,279.12 USD / year
…Leadership Values and Expectations, including quality and excellent customer service and here to learn more about San…
Added 3 mins ago
[US] Electronic Engineer
EdgeCortix
Remote, United States
EdgeCortix seeks to hire a talented and experienced Electronic Engineer to join our US based team and lead the design and development of our board level hardware products, including PCBAs…
Added 3 mins ago
Electrical Commissioning and Quality Field Engineer
Faith Technologies, Inc.
Menasha, WI · Clarksville, TN · Atlanta, GA · Monroe, LA · Olathe, KS
The QA/QC Field Engineer is a technical assistant to the field, acting as an internal liaison between the field, Project Management team, Preconstruction Team, and remote support teams. The…
Added 4 mins ago
Security Engineer II, AppSec Stores, Stores Security
Amazon.com Services LLC
Seattle, WA
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Added 4 mins ago
Software Development Engineer, SoC HAL
Annapurna Labs (U.S.) Inc.
Cupertino, CA
Annapurna Labs builds the custom silicon at the heart of AWS machine learning servers, and we are hiring a software engineer to help build the Hardware Abstraction Layer (HAL) that brings…
Added 7 mins ago
Member of Technical Staff, Forward Deployed
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Added 12 mins ago
Sr. Staff Systems Integration & Test Engineer Lead – APG 81 / Airborne Radar
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Added 12 mins ago
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Added 12 mins ago
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Baltimore, MD
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Baltimore, MD
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Added 12 mins ago
GA
Sr Manufacturing Engineer - Sourced Hardware
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Baltimore, MD
- $116,000 to $155,000 USD / year
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Added 12 mins ago
Advanced Lead Supplier Quality Engineer - Composites
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Baltimore, MD
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Added 15 mins ago
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…award-winning employment experience. As a Information Security Engineer working remote in US, you’ll be a part of bringing humanity to business.…
Added 15 mins ago
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Author technical reports and briefings, and present results to your team and the customer.
Added 15 mins ago
Network Engineer, Data Center Field Operations
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Google

Package Design Engineer

Sunnyvale, CA, United States

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Job details

Experience: 8 years of experience in chip package substrate design using Cadence APD or Mentor Expedition.
Posting language: English

Original job description

In most instances, this position requires in-person interviews as part of the hiring process.

Minimum qualifications:

Bachelor's degree in Mechanical Engineering, Material Engineering, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience.
8 years of experience in chip package substrate design using Cadence APD or Mentor Expedition.
Experience in chip package substrate layout, design verification, DFM and taping out for production.
Experience in design automation and scripting.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Experience in working with cross-functional teams including chip design, SI/PI, and PCB design teams.
Experience in 2.5D/3.5D advanced package design.
Experience in physical verification flow (LVS, DRC, connectivity).
Experience with CAD for creating simple mechanical drawings, such as package outline drawings (POD).
Ability to write scripts to customize elements of the Cadence or Mentor workflow.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Chip Package Designer on the Silicon Integration team, your role is to develop package substrate designs of advanced (2.5D/3.5D) packaging technologies for ML chips. This involves collaborating with SI/PI, Thermal/Mechanical, Assembly, and PCB engineers to create complex, high-performance substrate designs, where your goal is to optimize package substrate design for electrical performance, reliability, and assembly. You will manage all phases of the design process, including routing feasibility, test vehicle creation, product designs, conducting design reviews, artwork export, DFM process and generating final documentation. Additionally, you will be instrumental in identifying and incorporating advanced chip packaging technologies into the Google chip product design pipeline, which contributes to successful chip deployment in data centers, ensuring the best optimized PPA (Power, Performance, Area) designs and enhancing system performance relative to TCO (Total Cost of Ownership) and power. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Develop physical package substrate design of large form-factor package for ML high-performance computers (HPCs).
Develop and implement the methodology and CAD flow for efficient substrate design and enhanced productivity.
Manage and drive co-design initiatives across chip, package, and system levels, including securing production sign-off for package designs.
Collaborate closely with signal integrity/power integrity (SI/PI), thermal, and mechanical engineering teams to refine and optimize product package designs, test vehicles, and mock-up designs for product feasibility.
Define and document the requirements for the package substrate design and bill of materials (BOM).

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More about this job

Skills

Mechanical engineering
Electrical engineering
Computer engineering
Computer science
Printed circuit boards
Technical drawings
POD
Workflow
Design package
Packaging
ML
Assembly
Design process
Documentation
Google Cloud
Research

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