CPU RTL Design Engineer

In most instances, this position requires in-person interviews as part of the hiring process.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with microprocessor architecture.

Preferred qualifications:

• Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
• Experience with modern processor microarchitecture and related technologies and algorithms, through academic projects or industry experience.
• Knowledge of programming languages such as C, C++, and Python.
• Knowledge of general purpose operating systems such as Linux or Android.
• Knowledge of how to leverage AI to offload tasks to maximize productivity.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

• Contribute to CPU frontend design, emphasizing on microarchitecture and RTL design for a next generation CPU.
• Propose performance enhancing microarchitecture features with efficiency in mind. Work with architects and performance teams for trade-off studies. Communicate pros and cons of microarchitecture proposals. Facilitate final decision making by gathering necessary data and present to the larger team.
• Deliver designs meeting power, performance and area (PPA) goals with production quality. Become familiar with state-of-the-art techniques for memory subsystem design.
• Leverage design understanding in order to provide guidance to, and participate in, the performance modeling effort.
• Work closely with the functional verification team to ensure production quality designs, and with the physical design team to meet frequency, power, and area goals.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; Austin, TX, USA; Portland, OR, USA.