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Added 4 mins ago
Senior API & Integration Engineer
Vast Bank
Remote, United States
Vast Bank is looking to hire an Senior API & Integration Engineer!
Added 9 mins ago
IG
Building Engineer
Impec Group
Pleasanton, CA
- $40 to $50 USD / hour
Our client is seeking an experienced, hands-on Building Engineer to support the safe, efficient, and reliable operation of its corporate facilities. This position will lead maintenance…
Added 9 mins ago
ASIC Design Engineer, Cloud TPU
Google
Sunnyvale, CA
…designs, with a specific focus on TPU architecture and its integration within AI/ML-driven…
Added 24 mins ago
KC
Service System Engineer Mechanical/Optical
KLATencor Corporation
Ann Arbor, MI
- $97,000 to $164,900 USD / year
…across your area of expertise. PRIMARY RESPONSIBILITY: A Service Systems Engineer is responsible for driving design changes, sometimes fundamental ones, to optimize tool serviceability,…
Added 26 mins ago
Network Administrator 3/4 - TS/SCI - Dulles VA
Military Spouse Jobs & VetJobs
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Added 26 mins ago
2026 Associate/Electrical Engineer- Gilbert AZ
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Our Tactical Space Systems Division Integration and Test group is seeking an Electronics Engineer to join our team of qualified and diverse individuals in Gilbert, AZ. You will have the…
Added 43 mins ago
Senior Principal Systems Engineer (Electromagnetic Environmental Effects (E3))
CORP-Corporate Office
United States
Northrop Grumman Aeronautics Systems has an opening for a Senior Principal Systems Engineer (Electromagnetic Environmental Effects (E3)) to join our team of qualified, diverse individuals…
Added 43 mins ago
Principal Systems Engineer (Electromagnetic Environmental Effects (E3))
CORP-Corporate Office
United States
Northrop Grumman Aeronautics Systems has an opening for a Principal Systems Engineer (Electromagnetic Environmental Effects (E3)) to join our team of qualified, diverse individuals within…
Added 49 mins ago
Sr Consultant, Software Engineer (AI Engineer)
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Added 52 mins ago
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Added 52 mins ago
Senior Level Developer
Ignite IT
Remote, United States
Participate in structured discovery sessions to assess legacy systems, data flows, and integration dependencies.
Added 52 mins ago
Senior Network Security Engineer
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Added 52 mins ago
Senior AI/ML Engineer
Ignite IT
Remote, United States
Ignite IT Hub is seeking a senior AI/ML Engineer to maintain and enhance the U.S. Census Bureau's LLM Autocoder, which assigns standardized codes to survey write-in responses. You will…
Added 52 mins ago
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The Senior USPS Android Mobility & Unified Endpoint Management (UEM) Integration SME will lead technical activities required to integrate a Government Agency survey case-management mobile…
Added 52 mins ago
Senior Identity Engineer
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Remote, United States
Ignite IT is seeking an experienced Senior Identity and Access Management (IAM) Engineer to support enterprise identity and directory services for the U.S. Census Bureau.
Added 52 mins ago
Senior Systems Engineer
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El Segundo, CA
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Test Engineer
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ITEA Certified Test & Evaluation Professional and, or INCOSE Certified Systems Engineer Professional credentials.
Added 52 mins ago
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Added 52 mins ago
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El Segundo, CA
This program is supporting Government weapon systems program offices with subject matter experts that have a background with the Space-based and, or Ground Systems including Command &…
Added 52 mins ago
Senior Ground Segment Systems Engineer
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IESE Solutions is seeking an experienced Senior Ground Segment Systems Engineer to support to the US Space Force (USSF) in developing, deploying, and sustaining a National Security Space…
Added 52 mins ago
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This program is supporting Government weapon systems program offices with subject matter experts that have a background with the Space-based and, or Ground Systems including Command &…
Added 52 mins ago
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El Segundo, CA
This program is supporting Government weapon systems program offices with subject matter experts that have a background with the Space-based and, or Ground Systems including Command &…
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IESE Solutions is seeking a Systems Engineering Compliance Engineer to support the US Space Force (USSF) in developing and deploying novel command and control applications within the…

Google

ASIC Design Engineer, Cloud TPU

Sunnyvale, CA, United States

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Job details

Experience: 8 years of experience in RTL design.
Posting language: English

Original job description

In most instances, this position requires in-person interviews as part of the hiring process.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience in RTL design.
Experience with digital design and microarchitecture design.
Experience in optimizing for performance, power, and area.
Cross-functional experience with Design Verification (DV) and Physical Design (PD) teams.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
10 years of RTL design experience.
4 years of experience in power optimization and experience with power analysis tools like PowerArtist and PTPX.
Experience with Linting, CDC, RDC, LEC and experience with Scripting languages (i.e. Python or Perl).
Experience optimizing RTL solutions, RTL design methodologies and automate front-end engineering flows.
Experience in design automation, architecting RTL solutions and ASIC Synthesis flows.

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Join the team designing and developing the On-Chip Network of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in datacenters. You will be responsible for the microarchitecture, design, implementation, and integration of key digital logic blocks within the TPU. Your role requires close collaboration with cross-functional teams, including Verification, Physical Design, Validation, and Firmware, to deliver cutting-edge hardware. You will own critical design deliverables, help with integration efforts, and contribute to the continuous improvement of our design methodologies and flows. As an RTL Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design, computer architecture, and RTL coding to create innovative and efficient hardware solutions.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Define and document the microarchitecture for digital designs within the TPU.
Partner with Verification to develop test plans and debug RTL, and collaborate with Physical Design to achieve timing, area, power, and manufacturability goals.
Drive critical power optimization and automation initiatives across all on-chip-network components and subsystems.
Support post-silicon validation and hardware debugging efforts to ensure successful deployment.
Lead the development and enhancement of internal design tools, flows, and engineering methodologies.

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More about this job

Skills

Electrical engineering
Computer engineering
Computer science
RTL
Python
Perl
ML
Collaboration
Firmware
Process improvement
Google Cloud
Research
Debugging

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