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General Dynamics Mission Systems, Inc

FPGA Design Verification Engineer

Dedham, MA, United States

Combined Salary Range USD $119,941.00 - USD $133,000.00 /Yr.

Apply on careers-gdms.icims.com About employer

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Job details

Pay: Combined Salary Range USD $119,941.00 - USD $133,000.00 /Yr.
Apply by: Nov 13, 2027
Posting language: English
Posted: Nov 13, 2026

Original job description

Basic Qualifications

Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 2 years of relevant experience; or Master's degree, plus 6 months of relevant experience.

CLEARANCE REQUIREMENTS:Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

Responsibilities for this Position

We encourage you to apply if you have any of these preferred skills or experiences:

SystemVerilog & UVM: Good foundational knowledge of SystemVerilog object-oriented programming and Universal Verification Methodology (UVM) concepts.
Testbench Architecture: Good foundational knowledge of UVM Testbench Architectures.
Component Development: Comfortable using and developing UVM testbench components such as UVM agents, bus functional models, Reference Models, Scoreboards, etc.
Test Generation: Comfortable using and developing UVM sequences and constrained random tests.
Simulation Tools: Good understanding of RTL simulation tools (such as Siemens Questa Advanced Functional Verification tools) within a Linux Environment.
Regression & Debug: Comfortable executing tests/regressions, debugging testbench/DUT issues, and analyzing simulation results.
Automation & Scripting: Basic proficiency with scripting languages like Python, Tcl, or Linux shell scripting.

Familiarity with the following are also helpful:

Vendor Ecosystems: Experience developing UVM testbenches for designs implemented in Xilinx devices with Xilinx IP and SoCs.
Protocols: Exposure to AXI protocols, PCIe, Ethernet interfaces, or Xilinx SoC ecosystems.
Verification IP: Any familiarity with Questa Verification IP (QVIP).
Metrics & Assertions: Familiarity with functional/code coverage, cover points, and writing basic assertions.
Advanced Methods: Exposure to the Register Abstraction Layer (RAL) or Formal Verification tools.
Traceability: Familiarity with requirements-based verification, requirement tracing, and developing requirement verification strategies.
Hardware Lab Work: Experience debugging FPGA hardware and assisting with HW/SW integration.
Version Control: Familiarity with GIT and GitLab is a plus.

Duties and Tasks:

Build New Environments: Actively participate in the definition, design, and documentation of new FPGA verification environments.
Test Execution & Debug: Run simulations and regressions, debug testbench or Design Under Test (DUT) issues, and analyze simulation results.
Plan Creation: Work with design/system/SW/DV team as required to understand requirements and create test and simulation plans that establish clear functional criteria.
Automation: Write or maintain scripts to automate verification workflows.
Project Impact: Take ownership of verifying specific FPGA features and contribute directly to successful project releases.

General Knowledge, Skills, and Abilities:

Growth Mindset: Ability to work independently or in a small team environment and learn advanced verification methodologies using all available resources to stay abreast of technology and verification methodology trends.
Engineering Fundamentals: Good foundational understanding of FPGA design and verification concepts.
Problem Solving: Ability to think creatively to find bugs and edge cases in complex designs.
Communication: Clear written and verbal communication skills to effectively work with cross-domain teams.
Agility: Ability to multi-task and work in a dynamic environment that includes working with changing needs and requirements.

Salary Note This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled. Combined Salary Range USD $119,941.00 - USD $133,000.00 /Yr. Company Overview

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans

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Jobs in the United States