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Added 19 hours ago
Senior DSP/SDR Engineer
The Aerospace Corporation
Chantilly, VA
Experience in developing and implementing DSP algorithms in embedded environments for deliverable systems on either CPU or FPGA-based platforms
Added 1 day ago
Architectural Lead, Teradata Hardware Platform
Teradata
Jefferson City, MO
+ Act as design authority for future platform generations, making and documenting key trade-offs among performance, density, reliability, serviceability, and total cost of ownership.
Added 1 day ago
Low Latency Trading Infrastructure Engineer
Citigroup
Jacksonville, FL
…infrastructure, including OS optimization, kernel bypass technologies, CPU isolation, NUMA optimization, interrupt tuning, and deterministic performance…
Added 1 day ago
C
Senior Software Engineer - Platform
Calder
Redwood City, CA
- $179,000 to $250,500 USD / year
You'll architect and scale the infrastructure that processes terabytes of 3D data daily, ensuring reliability, cost efficiency, and fast iteration for the engineering teams that depend on…
Added 1 day ago
IC
Senior AI Software Development Engineer
Intel Corporation
OR · TX
- $133,410 to $240,710 USD / year
…communication software stack powering the world's largest AI and High-Performance Computing (HPC) workloads. As a Senior AI Software Development Engineer, you will architect, develop, and…
Added 1 day ago
ND
Technical Architect
NTT Data Americas, Inc.
Mahwah, NJ
- $80 to $84 USD / hour
We are currently seeking a Technical Architect to join our team
Added 1 day ago
J
CAS/COTS Systems Integration Engineer
Jobot
Atlantic City, NJ
- $150,000 to $175,000 USD / year
Diagnose system performance and latency issues across CPU, memory, storage I/O, networking, virtualization, applications, and remote displays.
Added 1 day ago
Senior Salesforce Developer
MedSpeed
Elmhurst, IL
Security & Performance at Scale: Thorough mastery of Salesforce sharing architecture, record-level security, Large Data Volumes (LDV), and CPU/heap governor limit optimization.
Added 2 days ago
Hardware Development Engineer II, AWS Mainstream Compute
Amazon
Seattle, WA
…develop creative and new designs that set the standards on performance, quality, cost, and operational…
Added 2 days ago
ZT
2027 Summer Internship (US) - Software/AI Engineer (Handheld Mobile Computers)
Zebra Technologies
Holtsville, NY
- $33 to $40.5 USD / hour
On-Device Telemetry Integration: Interface with Android system APIs and platform frameworks to capture real-time CPU, battery, and thermal sensor metrics.
Added 2 days ago
Lead Kubernetes Architect (AKS and GKE)
Humana
Lansing, MI
Lead the optimization of Kubernetes resources , including CPU, memory, storage, node pools, autoscaling policies, and workload scheduling to maximize efficiency and platform performance.
Added 2 days ago
Cloud Solution Engineer (Genomics & AI)
Oracle
Jefferson City, MO
+ Architect CPU and GPU computing, storage, networking, and data platforms on OCI. Benchmark accelerated genomics and model training or inference against customer baselines for accuracy,…
Added 2 days ago
Senior Backend Software Engineer
Flexcompute Inc.
Madison, WI
Optimize and manage high-performance computing clusters equipped with high-speed interconnects
Added 2 days ago
AI & HPC Infrastructure Engineer
Accenture
Saint Louis, MO
+ Architect and deploy with NVIDIA platform tools including Base Command Manager (BCM), NGC, NCCL, NVLink, and CUDA along with LLM inference engines (TensorRT-LLM), production serving…
Added 2 days ago
Senior Software Engineer - Kubernetes platform
Cloudflare
Austin, TX · Denver, CO · NY · San Francisco, CA · Washington, DC
…every request. As a result, they see significant improvement in performance and a decrease in spam and other attacks. Cloudflare was named to Entrepreneur Magazine’s Top Company Cultures…
Added 2 days ago
Embedded Software Engineer II
Brady Corporation
Boston, MA
Brady Engraving Solutions is seeking an Embedded Software Engineer to design, architect, and maintain high-performance embedded systems and edge-compute platforms for our next-generation…
Added 2 days ago
AWS Cloud/Linux Engineer
Atlas Technologies Inc
Alexandria, VA · AL · FL · GA · KS · KY · LA · ME · OR · RI · SC · TX · VA · WV · NJ · DC
…repositories, storage, networking, services, and kernel/system performance…
Added 2 days ago
Power Modeling Architect (CPU/GPU Accelerators)
Advanced Micro Devices, Inc
Austin, TX
…decision‑grade models for AMD's most advanced energy‑efficient high‑performance CPU cores, graphics, and machine‑intelligence chips. The team collaborates broadly across AMD, engaging on…
Added 2 days ago
Director - Ultra Low-latency Trading System Architect
RBC Capital Markets, LLC
NY
Kernel Bypass & OS-Level Optimization: Architect the system to bypass the kernel network stack entirely using technologies like DPDK (Data Plane Development Kit), Open Onload, or similar…
Added 3 days ago
A
Design Verification Engineer
Apple
Cupertino, CA
- $174,149 to $225,300 USD / year
Understanding of CPU architecture and system-level behavior to architect robust, high-quality verification strategies.
Added 3 days ago
A
Formal Validation Engineer
Apple
Cupertino, CA
- $207,673 to $277,600 USD / year
…verification for single or multiple design blocks and IP’s (CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP,…
Added 3 days ago
Lead Software Architect Compute Platform [SOC]
Stellantis
Auburn Hills, MI
…application interfaces, and vehicle-level software integration. The architect works closely with System, EE, Hardware, Controls, Safety, Cybersecurity, and Software teams to ensure…
Added 3 days ago
CPU Performance Architect
Google
Mountain View, CA
Partner closely with lead CPU architects and cross-functional teams to define dynamic, realistic power and performance goals for future Google silicon.
Added 3 days ago
Principal Power Electrical Engineer
Oracle
Santa Clara, CA · Burlington, MA
Experience with the power requirements of high performance CPU processors, GPUs, DDR memory DIMMs, PCIe Cards, Flash modules, disk drives etc.
Added 3 days ago
Sr. CPU Performance Architect
US Tech Solutions
Santa Clara, CA
We are looking for CPU Performance Engineer. The candidate will take part

Delos Data Inc

ASIC Architect

Palo Alto, CA, United States

$160,000 to $280,000 USD / year

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Job details

Pay: $160,000 to $280,000 USD / year
Experience: 7+ years of experience in ASIC architecture, micro-architecture, or high-level design.
Posting language: English
Posted: Oct 30, 2026

Original job description

ASIC ARCHITECT

We are seeking a highly skilled and visionary ASIC Architect to define, architect, and guide the development of next-generation, high-performance ASICs. As a key technical leader, you will translate high-level system requirements into detailed architectural specifications, balancing power, performance, and area (PPA) trade-offs.

Who we are:

We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.

The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.

Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.

What we need:

You will work across teams to define the architecture for IP blocks, sub-systems, and full SoC integration for advanced AI accelerators, networking, and datacenter computing workloads.

Key Responsibilities:

Lead the creation of Architectural Design Specifications (ADS) and Micro-architecture Specifications (MAS) for complex ASICs including high-speed interconnect fabric and IO protocols (Ethernet, PCIe, UCIe).
Develop high-level performance models (using SystemC/TLM, C++, or Python) to analyze workload behaviors and validate architectural assumptions.
Optimize chip-level and block-level architecture to meet stringent power, performance, and area goals.
Partner with RTL design, verification, physical design, firmware, and software teams to ensure seamless implementation and validation.
Drive architectural trade-off studies and lead design reviews.
Define advanced power management strategies including DVFS, power domains, and clock gating.
Mentor junior engineers and contribute to technical leadership across the organization.

Required Skills and Qualifications:

Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science
7+ years of experience in ASIC architecture, micro-architecture, or high-level design.
Strong proficiency in SystemVerilog/Verilog and C/C++ or SystemC for modeling.
Deep knowledge of computer architecture, including CPU/GPU cores, caches, fabric, and memory hierarchies.
Experience with industry-standard protocols such as Ethernet, PCIe or UAL.
Familiarity with EDA tools such as Synopsys Design Compiler, Cadence Genus, or similar.
Experience with performance modeling and analysis tools.

Desired Skills:

Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
Experience designing AI/ML accelerators or high-performance networking silicon.
Proven record of shipping high-performance silicon from concept to tape-out.
Familiarity with pre-silicon emulation platforms.
Strong scripting skills (Python, Tcl, Perl) for automation.
Excellent communication skills and ability to articulate complex architectural concepts.
Proactive problem solver capable of working with minimal oversight.
Strong leadership and mentorship capabilities

Compensation:

Target base salary for this role is $160,000 - $280,000 per year + meaningful equity + benefits + 401k. Our salary ranges are determined by role, level, experience, and location.

Agency Note:

We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.

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More about this job

Skills

Electrical engineering
Computer engineering
Computer science
SystemVerilog
Verilog
C
C++
EDA
Synopsys Design Compiler
ML
Python
Perl
Communication skills
Leadership

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