Jobs in the United States

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Added 1 hour ago
Digital ASIC/FPGA Design Engineer II - Onsite
RTX Corporation
mckinney, TX
Raytheon is seeking a motivated Digital Design Engineer to support product development for defense applications. This position is based in McKinney, Texas .
Added 1 hour ago
Digital ASIC/FPGA Design Engineer I (Onsite)
RTX Corporation
mckinney, TX
Raytheon is seeking a motivated Digital Design Engineer to support product development for defense applications. This position is based in McKinney, Texas .
Added 20 hours ago
RTL-to-GDS implementation, Senior Principal Solutions Engineer
Cadence
United States
In addition, Solutions Engineers are expected to be able to articulate design methodologies involving Cadence tools and be 'elevator talk' proficient in the full Cadence tool portfolio.…
Added 21 hours ago
ASIC Design Automation Engineer
Avago Technologies Wireless (U.S.A.) Manufacturing LLC
United States
Broadcom’s ASIC Products Division is seeking a Design Automation Software Development Engineer. They will define, develop, deploy and support the methodology, design automation software…
Added 21 hours ago
ASIC Design Engineer
Avago Technologies U.S. Inc.
United States
Contribute to design flow improvements, automation, and deep sub-micron methodology development.
Added 21 hours ago
Physical Design Engineer
LSI Corporation
United States
Hands on experience with timing analysis and place and route tools for ASIC/ SoC Design is a must.
Added 1 day ago
ASIC Design - Floorplan Engineer
Avago Technologies U.S. Inc.
United States
Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for…
Added 1 day ago
Senior ASIC Design Verification Engineer - Slingshot
Hewlett Packard Enterprise
Chippewa Falls, WI · Ft. Collins, CO · Bloomington, MN
In this role you will be responsible for all phases of pre-silicon design verification, including design verification methodology, test-plan development, testbench development, coverage…
Added 1 day ago
Senior VLSI Tools and Methodology Engineer
Hewlett Packard Enterprise
Ft. Collins, CO · Spring, TX · Chippewa Falls, WI
Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for…
Added 1 day ago
ASIC Design Verification Engineer - Slingshot
Hewlett Packard Enterprise
Ft. Collins, CO · Bloomington, MN · Chippewa Falls, WI
In this role you will be responsible for all phases of pre-silicon design verification, including design verification methodology, test-plan development, testbench development, coverage…
Added 1 day ago
Senior Principal Engineer, Physical Designer
MSI - (Marvell Semiconductor Inc.) US
Santa Clara, CA
Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual…
Added 1 day ago
Senior Design Verification Engineer
Blue Origin Personnel, LLC
Cupertino, CA
As a Senior Verification Engineer on the ASIC & Networking team, you support TeraWave's first in-house silicon program, which comprises a high-throughput modem and a DSP-intensive digital…
Added 2 days ago
VLSI Physical Design Engineer
Hewlett Packard Enterprise
Ft. Collins, CO · Chippewa Falls, WI · Bloomington, MN
Review design and project activities for compliance with ASIC technology, methodology, and development standards.
Added 2 days ago
Engineer II - Physical Design
Microchip - USA
Chandler, AZ
Join the Physical Design team as a Engineer II-Physical Design supporting semiconductor synthesis, floorplanning, placement, clocking, routing, timing, power, physical verification,…
Added 2 days ago
Module Advanced Development Signal Integrity Engineer
Nokia of America Corporation
Allentown, PA
Added 2 days ago
Lead ASIC Design Verification Engineer
Chelsea Search Group
Minneapolis, MN
A Lead ASIC Design Verification Engineer will establish, staff, and lead our ASIC verification team. This is a hands-on technical leadership role – you will personally architect and build…
Added 2 days ago
Lead Design Verification Engineer
Chelsea Search Group
Minneapolis, MN
A Lead ASIC Design Verification Engineer will establish, staff, and lead our ASIC verification team. This is a hands-on technical leadership role – you will personally architect and build…
Added 2 days ago
Lead UVM Design Verification Engineer
Chelsea Search Group
Minneapolis, MN
A Lead ASIC Design Verification Engineer will establish, staff, and lead our ASIC verification team. This is a hands-on technical leadership role – you will personally architect and build…
Added 2 days ago
Wireless SOC Verification Engineer
Apple
Sunnyvale, CA
…high speed layered protocols, low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on Wireless protocols, FW-HW interactions, and complexities of…
Added 2 days ago
Wireless SOC Verification Engineer
Apple
Sunnyvale, CA
…high speed layered protocols, low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on Wireless protocols, FW-HW interactions, and complexities of…
Added 2 days ago
Wireless SOC Verification Engineer
Apple
Irvine, CA
…high speed layered protocols, low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on Wireless protocols, FW-HW interactions, and complexities of…
Added 2 days ago
Wireless SOC Verification Engineer
Apple
Irvine, CA
…high speed layered protocols, low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on Wireless protocols, FW-HW interactions, and complexities of…
Added 2 days ago
Wireless SOC Verification Engineer
Apple
San Diego, CA
…high speed layered protocols, low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on Wireless protocols, FW-HW interactions, and complexities of…
Added 2 days ago
Wireless SOC Verification Engineer
Apple
San Diego, CA
…high speed layered protocols, low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on Wireless protocols, FW-HW interactions, and complexities of…
Added 2 days ago
IG
Senior ASIC Design Engineer
Insight Global
Vancouver, WA
- $116,000 to $180,000 USD / year
One of Insight Global’s clients is seeking a Senior ASIC Design Engineer to join its R&D engineering team in Vancouver, WA. This individual will be a senior, hands-on contributor…

Cisco Systems, Inc.

ASIC DFT Engineer

Austin, TX, United States
San Jose, CA, United States

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Job details

Apply by: Dec 18, 2026
Experience: Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 7 years of experience.
Posting language: English
Posted: Oct 28, 2026

Original job description

The application window is expected to close on: 12/17/2026Meet the Team:

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms - like Silicon One - are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development - from design to qualification to production - is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Your Impact:

You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

Minimum Qualifications:

Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 7 years of experience.
Prior experience working in the latest innovative trends in DFT, test and silicon engineering.
Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
Prior experience working with Gate level simulation, debugging with VCS and other simulators.
Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687

Preferred Qualifications:

Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification
DFT CAD development - Test Architecture, Methodology and Infrastructure
Test Static Timing Analysis
Post silicon validation using DFT patterns.
Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design

Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $139,300.00 to $203,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and
Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:

$167,700.00 - $282,000.00

Non-Metro New York state & Washington state:

$149,100.00 - $250,900.00

For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

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