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Added 1 min ago
Structural Restoration Consultant/Engineer
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Internal conferences and professional development opportunities
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Post Market Surveillance Engineer II
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…questions and regularly check for understanding in support in your development as a Post Market Surveillance Engineer…
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Quality Engineer
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Software Engineer III - Node.js and TypeScript
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Salesforce DevOps Engineer
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- $86,800 to $198,000 USD / year
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Modernization Systems Engineer
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- $31,533 USD / year
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Senior Engineer, Advanced Engineering
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Senior Product Development Engineer
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Staff Product Development Engineer
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- $123,612 to $154,515 USD / year
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Added 6 mins ago
Sr. Specialist, Quality Assurance
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The Senior Quality Assurance Specialist/Engineer serves as a key leader in maintaining and continuously improving the organization’s Quality Management System (QMS). This role is…
Added 7 mins ago
Principal Software & Controls Engineer
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Manufacturing Quality Engineer
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Sr. Engineer, Embedded Engineering-1131
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…use LinuxOS concepts including processes, scheduling, inter-process communication, and multithreading; perform version control using Git; build CI/CD pipelines using Jenkins; use test tools…
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Lead Industrial Engineer
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WSP is currently initiating a search for a Senior Mechanical Engineer to work out of Denver, CO or Arlington, VA.
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Our Caterpillar Remanufacturing Division currently has an opening for a Manufacturing Engineer Technician I position located in the Corinth, MS facility. This position will ensure…
Added 10 mins ago
Forward Deployed Robotics & Systems Engineer
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Decision Making and Critical Thinking: Knowledge of the decision-making process and associated tools and techniques; ability to accurately analyze situations and reach productive decisions…
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Lead Forward Deployed Robotics & Systems Engineer
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Own technical readiness for complex deployments within the site readiness process run by the Field Deployment Program Manager, including accountability for site network and RTK…
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Senior Forward Deployed Robotics & Systems Engineer
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Serve as the technical authority for assigned deployments, supporting the Machine & Site Engineer as the named site owner and customer contact, and translating field evidence into…
Added 11 mins ago
Full Stack Software Engineer – Generative AI
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Strong Python development skills with experience building maintainable, testable production applications.
Added 11 mins ago
Sr. Engineer, Systems - Defined Term
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The Sr. Systems Engineer will be responsible for providing technical input to a team of systems and cross-functional engineers. You will support the development and improvement of on-market…

Chelsea Search Group

Senior Principal Physical Implementation Engineer

Remote, United States

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Job details

Experience: 10+ years of direct industry experience with ASIC and/or SoC design.
Posting language: English
Posted: Nov 10, 2026

Original job description

Senior Principal Physical Implementation Engineer

Job Description:

We are seeking an experienced Physical Design / P&R Engineer to take a key role in delivering complex, high-performance ASICs from RTL/netlist through GDSII and tapeout. You’ll own critical aspects of physical implementation, including floorplanning, placement, CTS, routing, timing closure, and PPA optimization, working with advanced technologies such as RISC-V, DDR, and SerDes. Using industry-leading tools including Synopsys Fusion Compiler and Siemens Calibre, you’ll solve challenging physical design problems and help drive successful silicon outcomes. This is an opportunity to make a significant technical impact while collaborating with a highly experienced, multidisciplinary ASIC engineering team.

Essential Duties and Qualifications:

Analyze and optimize designs to meet power, performance, and area (PPA) objectives while satisfying timing, signal integrity, reliability, and manufacturability requirements.
Collaborate closely with RTL design, verification, DFT, analog/mixed-signal, packaging, and other engineering teams to ensure successful chip integration.
Develop and optimize floorplans incorporating complex IP and high-speed interfaces, including DDR and SerDes.
Develop, maintain, and improve physical design flows, scripts, methodologies, and automation to increase efficiency and design quality.
Identify and resolve congestion, routing, timing, power integrity, and physical verification issues throughout the implementation process.
Participate in design reviews and provide recommendations regarding floorplanning, physical architecture, implementation strategy, and PPA tradeoffs.
Perform full-chip physical design implementation from synthesized netlist through GDSII, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, optimization, and timing closure.
Perform physical verification and signoff activities using Siemens Calibre, including DRC and LVS verification and resolution of physical design violations.
Perform static timing analysis and drive timing closure across multiple operating modes, process corners, and design constraints.
Provide technical guidance and mentoring to other engineers and contribute to the continued development of the team's internal physical design capabilities.
Support final design signoff and tapeout, ensuring all applicable physical design and verification requirements have been satisfied.
Support integration and physical implementation of third-party and internally developed IP blocks.
Support the physical implementation and integration of RISC-V processor-based designs and subsystems, including timing, power, and physical design considerations.
Troubleshoot complex implementation and signoff issues and drive corrective actions through resolution.
Utilize Synopsys Fusion Compiler for physical implementation, optimization, and design closure.

Qualifications:

10+ years of direct industry experience with ASIC and/or SoC design.
BSEE/MSEE or equivalent
Excellent problem-solving skills and attention to detail.
Experience with industry standard development tools and methodologies.
Familiarity with RISC architectures (e.g., ARM, MIPS).
Proficiency in Synopsys Design Compiler and other EDA tools.
Proven track record of first-pass successes.
Self-starter with the ability to assume leadership roles.
Strong background in RTL based digital IC design using Verilog/SystemVerilog
Strong understanding of digital design principles.
Willingness to mentor and develop less experienced engineers.

chelseasearchgroupcatsone

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Skills

RTL
DFT
Packaging
Coaching
Troubleshoot
Problem solving
Attention to detail
Synopsys Design Compiler
EDA
Verilog
SystemVerilog
Design principles

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