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Added 14 mins ago
UO
Senior/Principal Electrical Engineer - Spacecraft and Instruments
University of Colorado Denver
Boulder, CO
- $34,986 USD / year
Select EEE parts; complete derating, worst-case, reliability, and circuit-performance analyses; and model designs using LTspice, PSpice, Ansys, or comparable simulation tools.
Added 14 mins ago
UO
Flight Software Simulation Engineer
University of Colorado Denver
Boulder, CO
- $34,986 USD / year
LASP is looking for a Flight Software Simulation Engineer to join the spacecraft simulator team for a deep space mission that will tour the inner solar system and explore the main asteroid…
Added 1 hour ago
UO
Assistant Director of Clinical Simulation
University of Colorado Denver
Aurora, CO
- $105,000 to $125,000 USD / year
Job Title: Assistant Director of Clinical Simulation (a faculty administrative appointment)/
Added 1 hour ago
UO
Senior FPGA Development Engineer
University of Colorado Denver
Boulder, CO
- $34,986 USD / year
Define and lead verification and validation activities, including requirements-based test planning, independent review, simulation, coverage, static analysis, clock and reset domain…
Added 1 hour ago
UO
Open Rank- Assistant, Associate, Professor
University of Colorado Denver
Aurora, CO
- $145,000 to $147,464 USD / year
…genome-scale biology, multiscale modeling, mathematical physiology, simulation, machine learning, artificial intelligence, human-computer interaction, data integration, and mathematical and…
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The Aerospace Corpor
Colorado Springs, CO
- $151,300 to $226,900 USD / year
Over 10 years of modeling, simulation, and analysis experience, with a strong background in space systems technologies, space architectural concepts or joint warfighting operations.
Added 2 hours ago
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The Aerospace Corpor
Colorado Springs, CO
- $129,000 to $249,600 USD / year
Familiarity with modeling and simulation tools such as STK and Visualyse
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Space Enterprise Optimization Analyst
The Aerospace Corpor
Colorado Springs, CO
- $86,600 to $150,400 USD / year
As part of SEDOD and EDS, a member of our technical staff will employ and develop sophisticated simulation tools to perform space and ground design, optimization, and analysis in support of…
Added 2 hours ago
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Space Enterprise Commercial Portfolio Optimization Leader
The Aerospace Corpor
Colorado Springs, CO
- $120,800 to $181,100 USD / year
Coordinatingand organizinganalysis effortsusingmodeling and simulation capabilities to capture both business and technical needs forenhancingnational architectures with commercial portfolios
Added 2 hours ago
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2027 Remote Sensing Architecture Performance Graduate Intern
The Aerospace Corpor
Colorado Springs, CO
- $32 to $48 USD / hour
…security and civil space enterprises,leveragingour modeling and simulation (M&S)expertiseto evaluateend-to-endarchitecture…
Added 2 hours ago
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2027 Remote Sensing Architecture Technical Engineer
The Aerospace Corpor
Colorado Springs, CO
- $100,000 to $140,000 USD / year
…security and civil space enterprises,leveragingour modeling and simulation (M&S)expertiseto evaluateend-to-endarchitecture…
Added 2 hours ago
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Flight Dynamics Engineer
The Aerospace Corpor
Colorado Springs, CO
- $132,900 to $249,600 USD / year
…design and optimization, and atmospheric flight modeling and…
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2027 Trajectory Optimization Engineer
The Aerospace Corpor
Colorado Springs, CO
- $86,600 to $150,400 USD / year
…design and optimization, and atmospheric flight modeling and simulation. The selected candidate will provide expertise for a wide range of customer flight mechanics needs, supporting…
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UO
Open Rank Regular Faculty: Assistant - Full Professor
University of Colorado Denver
Aurora, CO
- $110,000 to $150,000 USD / year
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CORP-Corporate Office
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Added 3 hours ago
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Allen Park, MI
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Chelsea Search Group

Lead Design Verification Engineer

Minneapolis, MN, United States

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Job details

Experience: 8+ years of ASIC/SoC verification experience, with demonstrated ownership of verification for at least one production tapeout.
Posting language: English
Posted: Nov 4, 2026

Original job description

Lead ASIC Design Verification Engineer

Job Description:

A Lead ASIC Design Verification Engineer will establish, staff, and lead our ASIC verification team. This is a hands-on technical leadership role – you will personally architect and build UVM testbenches for our current programs while simultaneously defining the verification methodology, infrastructure, and hiring plan that will scale the function from a single contributor to a full team. You will be the technical authority on verification – setting coverage-driven sign-off criteria, owning verification schedule and risk for tapeouts, and making the build-versus-buy calls on VIP, tools, and compute. If you have been the strongest verification engineer on someone else’s team and want to build your own, this is the role.

Key Responsibilities and Qualifications:

Technical Leadership

Define and own the ASIC verification methodology, standards, and sign-off criteria across company programs.
Architect UVM-based verification environments for digital SoCs, memory subsystems, secure boot and cryptographic subsystems, and die-to-die interfaces.
Establish reusable verification infrastructure - base classes, VIP strategy, scoreboarding and checker architecture, register abstraction (UVM RAL), and coverage models - designed for reuse across programs and derivative parts.
Own verification planning: testplan development, coverage closure strategy, regression architecture, and quantitative sign-off metrics reported to program and customer stakeholders.
Serve as the verification voice in design and architecture reviews, and as the technical interface to customers, primes, and government stakeholders on verification approach and evidence.

Team Building

Onboard, mentor, and technically develop verification engineers, including junior engineers and design engineers transitioning into verification.
Define team structure, roles, and hiring profiles for the verification organization; participate directly in recruiting, interviewing, and selection.
Establish and enforce code review, revision control, documentation, and traceability practices appropriate to defense-qualified deliverables.
Allocate verification effort across concurrent programs and communicate resourcing risk to engineering and program management.

Hands-On Execution

Write SystemVerilog/UVM testbench code, sequences, agents, and functional coverage models - this role is expected to remain approximately 50–70% hands-on.
Drive constrained-random and directed verification to coverage closure; triage failures and drive root-cause resolution with designers.
Apply complementary methods where they are the right tool: formal property verification, assertion-based verification (SVA), gate-level simulation, and emulation/prototyping.
Support verification of radiation-hardening and fault-tolerance features, including TMR structures, error detection and correction, and SEU/SET mitigation behavior.
Support post-silicon bring-up by correlating silicon behavior to pre-silicon models and closing verification gaps.
Own and maintain regression infrastructure, simulation licensing and compute utilization, and CI for verification.

Required Qualifications:

B.S. in Electrical Engineering, Computer Engineering, or Computer Science.
8+ years of ASIC/SoC verification experience, with demonstrated ownership of verification for at least one production tapeout.
Expert-level SystemVerilog and UVM. You have architected UVM environments from scratch - not only extended environments built by others.
Strong command of constrained-random verification, functional coverage, coverage-driven closure, and assertion-based verification with SVA.
Experience with commercial simulation and coverage tools (Synopsys VCS/Verdi, Cadence Xcelium, and/or Siemens Questa) and with regression management at scale.
Working knowledge of digital design and RTL - sufficient to read, reason about, and debug a designer's code, and to argue productively about intent versus implementation.
Scripting proficiency for verification infrastructure (Python, Perl, TCL, and shell) and fluency with Git-based workflows and Linux development environments.
Demonstrated technical leadership: mentoring engineers, leading a verification effort, or owning verification schedule and sign-off for a program.
Clear written and verbal communication - including the ability to present verification status and evidence to non-verification stakeholders and customers.
U.S. Citizenship is required due to ITAR and DFARS requirements applicable to our programs, along with the ability to obtain and maintain a U.S. Government security clearance.

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Skills

Leadership
Documentation
Program management
SystemVerilog
Electrical engineering
Computer engineering
Computer science
RTL
Python
Perl
Git
Linux
Coaching
Communication skills

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