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Added 1 day ago
Development Engineer, System Integration AD
Mercedes-Benz
San Jose, CA
Debug issues especially on the communication between ADAS and rest of vehicle ECUs via signal chain analysis.
Added 2 days ago
Senior (DevOps) Machine Learning Engineer - Federal
ServiceNow, Inc.
Santa Clara, CA
It all started when engineer Fred Luddy wrote code that automated a tedious task for his coworker, Phyllis. She cried tears of joy. That moment inspired Fred to build a company that could…
Added 3 days ago
Senior DevOps Engineer (Kubernetes) - Federal
ServiceNow
Santa Clara, CA
It all started when engineer Fred Luddy wrote code that automated a tedious task for his coworker, Phyllis. She cried tears of joy. That moment inspired Fred to build a company that could…
Added 8 days ago
Staff Software Engineer, Observability/Site Reliability
PsiQuantum
Palo Alto, CA
We are looking for a Staff Software Engineer to join the Observability team. You will wire up OpenTelemetry instrumentation and collection, run and scale Prometheus and Grafana, and turn…
Added 9 days ago
Senior Software Engineer, Data Infrastructure (RDBMS) (LATAM)
TRM Labs
Remote, United States
…and disrupt crime. TRM's platforms enable investigators to trace illicit activity, build cases, and construct operating pictures of threat networks. Leading agencies and businesses…
Added 17 days ago
Senior Staff Machine Learning Engineer - DevOps
ServiceNow
Santa Clara, CA
It all started when engineer Fred Luddy wrote code that automated a tedious task for his coworker, Phyllis. She cried tears of joy. That moment inspired Fred to build a company that could…
Added 18 days ago
Senior Software Engineer, Performance Engineering
Veeam Software
San Jose, CA
We are seeking a Senior Software Engineer to join the Performance Engineering team for Data Connectors & High-Scale Ingestion. You will own the throughput, latency, scalability, and…
Added 20 days ago
Lead Debug/Trace/Profiling Design Engineer
SiFive, Inc.
Austin, TX · Boston, MA
SiFive is seeking a hardware design technical lead who is passionate about designing industry-leading debug, trace and profiling IP to help drive the tidal wave of adoption of RISC-V as the…
Added 20 days ago
C
Senior Principal Software Engineer - Accelerated Verification IP
Cadence
United States
- $154,000 to $286,000 USD / year
Debug, logging, performance profiling, and compliance features
Added 20 days ago
E
SI/PI Engineer
Etched
San Jose, CA
- $250,000 to $400,000 USD / year
- Execute power delivery network (PDN) design and analysis: target impedance profiling, decoupling capacitor selection, AC/DC power analysis, and IR-drop simulation.
Added 20 days ago
H
Audio DSP Deployment Engineer
Hark
San Jose, CA
- $120,000 to $300,000 USD / year
We're looking for an experienced Audio DSP Deployment Engineer to own how our audio algorithms work on device. Our algorithm team prototypes and validates new audio processing on the…
Added 20 days ago
Senior Software Engineer, Database Engineer
TRM Labs
Remote, United States
…and disrupt crime. TRM's platforms enable investigators to trace illicit activity, build cases, and construct operating pictures of threat networks. Leading agencies and businesses…
Added 20 days ago
Senior Software Engineer, Data Infrastructure (RDBMS)
TRM Labs
Remote, United States
…and disrupt crime. TRM's platforms enable investigators to trace illicit activity, build cases, and construct operating pictures of threat networks. Leading agencies and businesses…

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Cadence

Senior Principal Software Engineer - Accelerated Verification IP

United States

$154,000 to $286,000 USD / year

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Job details

Pay: $154,000 to $286,000 USD / year
Apply by: Dec 31, 2026
Experience: BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
Posting language: English
Posted: Jul 15, 2026

Original job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The AVIP (Accelerated Verification IP) and Virtual Bridge (VB) business is a core part of Cadence’s Virtual Emulation and System Verification portfolio, enabling high‑performance verification on Palladium and Protium platforms. The team builds high‑performance protocol solutions that enable customers to verify complex SoCs and systems at much higher speed and scale than traditional simulation.

Together, AVIP and VB are critical to customers building high‑performance compute, AI, networking, and memory‑coherent systems, where early software bring‑up, performance analysis, and protocol compliance are essential.

The AVIP / Virtual Bridge R&D team designs, implements, and productizes protocol solutions that span hardware, software, and system‑level verification. The team works across multiple layers, including:

Protocol architecture and feature definition
High‑performance transactor and BFM development
Hardware‑software co‑simulation and emulation flows
Debug, logging, performance profiling, and compliance features
Customer enablement, escalations, and interoperability validation

The team supports a broad portfolio of industry‑standard protocols, such as PCIe, CXL, Ethernet, USB, UCIe, and emerging interconnects, and works closely with emulation platform teams, controller/PHY teams, and customers.

This role will contribute directly to the development and enhancement of PCIe/CXL AVIP and/or PCIe/CXL Virtual Bridge products, focusing on protocol functionality, performance, and robustness. Depending on the specific protocol area, the work may involve:

Implementing PCIe protocol features and state machines
Enhancing performance and scalability on emulation platforms
Developing debug, trace, and analysis capabilities
Supporting system‑level and software‑driven use cases via PCIe Virtual Bridge
Working with customers and field teams to resolve issues and deliver solutions related to PCIe and CXL

In this role, the engineer will be responsible for designing, developing, and maintaining PCIe/CXL AVIP/VB components as part of a larger protocol solution. The role is hands‑on and spans feature development, validation, and customer readiness.

Key responsibilities include:

Designing and implementing protocol functionality in PCIe AVIP and/or Virtual Bridge components
Developing and debugging BFMs, transactors, and associated software interfaces
Ensuring correctness, performance, and scalability in emulation and acceleration flows
Collaborating with cross‑functional teams
Participating in feature bring‑up, regression, and release activities
Supporting customer issues, reproducing problems, and delivering fixes

What you’ll need

BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
Strong fundamentals in digital design, computer architecture, and system‑level verification
Experience with hardware description languages (SystemVerilog/Verilog) and/or C/C++
Understanding of standard interconnect or IO protocols (e.g., PCIe, CXL, NVMe)
Familiarity with emulation, acceleration, or hybrid verification flows is a strong plus
Good debugging skills using waveforms, logs, and protocol analyzers
Ability to work across hardware and software boundaries

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t.

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Skills

Regulatory compliance
Debugging
SystemVerilog
Verilog
C
C++

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