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Senior Thermal Engineer, Spacecraft
EnduroSat
Denver, CO
- $110,000 to $160,000 USD / year
We are EnduroSat! A fast-growing space scale-up at the forefront of satellite innovation, specializing in advanced software-flexible satellites for commercial, governmental, and scientific…
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Software Test Engineer II
Wabtec
Germantown, MD
This is an early-career Software Test Engineer II position intended for engineers with a minimum of two years of relevant experience in embedded systems and software validation. The…
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Geospatial Project Manager / Utility Locating
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Minnetonka, MN
- $85,000 to $110,000 USD / year
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Geospatial Project Manager / Utility Locating
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Westminster, CO
- $85,000 to $110,000 USD / year
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Principal AI Architect
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United States
…pharmacy automation with solutions such as the NEXiA® Enterprise Software Suite, enabling pharmacists to focus more on patient care while improving operational…
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Chicago, IL
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Utility Network GIS Consultant, Manager
PWC US
TX-Houston, TX · IN-Indianapolis, IN · NC-Raleigh, NC · NC-Charlotte, NC · GA-Atlanta, GA · IL-Chicago, IL · TX-Austin, TX · DC-Washington, DC · OH-Cincinnati, OH · OH-Columbus, OH · TX-Dallas, TX · NV-Las Vegas, NV · CA-Los Angeles, CA · MD-Baltimore, MD · CO-Denver, CO · MA-Boston, MA · CA-Sacramento, CA · NJ-Florham Park, NJ · UT-Salt Lake City, UT · NY-New York, NY · CA-San Francisco, CA · PA-Philadelphia, PA · PA-Pittsburgh, PA
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Application Developer
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Annapolis Junction, MD
Reflexive Concepts is seeking an Application Developer to join our team!
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Experience with version control software like Git and Subv
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Tax Intern
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Software Developer III
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Astera Labs

Principal Digital Design Engineer

San Jose, CA, United States
CA, United States

The base salary range is $185,000.00 USD – $230,000.00 USD.

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Job details

Pay: The base salary range is $185,000.00 USD – $230,000.00 USD.
Experience: +8 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage.
Posting language: English
Posted: Nov 2, 2026

Original job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description

We are looking for Principal Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.

Basic Qualifications:

Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.
+8 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage.
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
Authorized to work in the US and start immediately.

Required Experience:

Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production
Experience with Synopsys and/or Cadence digital design tools/flows
Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
Familiarity with UVM based design verification
Silicon bring-up and debug expertise
Small-geometry CMOS (≤28nm) design

Preferred Experience:

Firmware development with C-language, scripting with Python or other equivalent programming languages.
Development/support for PCIe or Ethernet Switch products.

The base salary range is $185,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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More about this job

Skills

RTL
Communication skills
Electrical engineering
DFT
GDS
Firmware
C
Python
Programming languages

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