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Added 15 hours ago
RTL-to-GDS implementation, Senior Principal Solutions Engineer
Cadence
United States
In addition, Solutions Engineers are expected to be able to articulate design methodologies involving Cadence tools and be 'elevator talk' proficient in the full Cadence tool portfolio.…
Added 15 hours ago
ASIC Design Automation Engineer
Avago Technologies Wireless (U.S.A.) Manufacturing LLC
United States
Broadcom’s ASIC Products Division is seeking a Design Automation Software Development Engineer. They will define, develop, deploy and support the methodology, design automation software…
Added 15 hours ago
ASIC Design Engineer
Avago Technologies U.S. Inc.
United States
Contribute to design flow improvements, automation, and deep sub-micron methodology development.
Added 15 hours ago
Physical Design Engineer
LSI Corporation
United States
Hands on experience with timing analysis and place and route tools for ASIC/ SoC Design is a must.
Added 20 hours ago
ASIC Design - Floorplan Engineer
Avago Technologies U.S. Inc.
United States
Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for…
Added 1 day ago
Senior ASIC Design Verification Engineer - Slingshot
Hewlett Packard Enterprise
Chippewa Falls, WI · Ft. Collins, CO · Bloomington, MN
In this role you will be responsible for all phases of pre-silicon design verification, including design verification methodology, test-plan development, testbench development, coverage…
Added 1 day ago
Senior VLSI Tools and Methodology Engineer
Hewlett Packard Enterprise
Ft. Collins, CO · Spring, TX · Chippewa Falls, WI
Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for…
Added 1 day ago
ASIC Design Verification Engineer - Slingshot
Hewlett Packard Enterprise
Ft. Collins, CO · Bloomington, MN · Chippewa Falls, WI
In this role you will be responsible for all phases of pre-silicon design verification, including design verification methodology, test-plan development, testbench development, coverage…
Added 1 day ago
Senior Principal Engineer, Physical Designer
MSI - (Marvell Semiconductor Inc.) US
Santa Clara, CA
Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual…
Added 1 day ago
Senior Design Verification Engineer
Blue Origin Personnel, LLC
Cupertino, CA
As a Senior Verification Engineer on the ASIC & Networking team, you support TeraWave's first in-house silicon program, which comprises a high-throughput modem and a DSP-intensive digital…
Added 1 day ago
VLSI Physical Design Engineer
Hewlett Packard Enterprise
Ft. Collins, CO · Chippewa Falls, WI · Bloomington, MN
Review design and project activities for compliance with ASIC technology, methodology, and development standards.
Added 1 day ago
Engineer II - Physical Design
Microchip - USA
Chandler, AZ
Join the Physical Design team as a Engineer II-Physical Design supporting semiconductor synthesis, floorplanning, placement, clocking, routing, timing, power, physical verification,…
Added 1 day ago
Module Advanced Development Signal Integrity Engineer
Nokia of America Corporation
Allentown, PA
Added 2 days ago
Lead ASIC Design Verification Engineer
Chelsea Search Group
Minneapolis, MN
A Lead ASIC Design Verification Engineer will establish, staff, and lead our ASIC verification team. This is a hands-on technical leadership role – you will personally architect and build…
Added 2 days ago
Lead Design Verification Engineer
Chelsea Search Group
Minneapolis, MN
A Lead ASIC Design Verification Engineer will establish, staff, and lead our ASIC verification team. This is a hands-on technical leadership role – you will personally architect and build…
Added 2 days ago
Lead UVM Design Verification Engineer
Chelsea Search Group
Minneapolis, MN
A Lead ASIC Design Verification Engineer will establish, staff, and lead our ASIC verification team. This is a hands-on technical leadership role – you will personally architect and build…
Added 2 days ago
Wireless SOC Verification Engineer
Apple
Sunnyvale, CA
…high speed layered protocols, low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on Wireless protocols, FW-HW interactions, and complexities of…
Added 2 days ago
Wireless SOC Verification Engineer
Apple
Sunnyvale, CA
…high speed layered protocols, low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on Wireless protocols, FW-HW interactions, and complexities of…
Added 2 days ago
Wireless SOC Verification Engineer
Apple
Irvine, CA
…high speed layered protocols, low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on Wireless protocols, FW-HW interactions, and complexities of…
Added 2 days ago
Wireless SOC Verification Engineer
Apple
Irvine, CA
…high speed layered protocols, low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on Wireless protocols, FW-HW interactions, and complexities of…
Added 2 days ago
Wireless SOC Verification Engineer
Apple
San Diego, CA
…high speed layered protocols, low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on Wireless protocols, FW-HW interactions, and complexities of…
Added 2 days ago
Wireless SOC Verification Engineer
Apple
San Diego, CA
…high speed layered protocols, low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on Wireless protocols, FW-HW interactions, and complexities of…
Added 2 days ago
IG
Senior ASIC Design Engineer
Insight Global
Vancouver, WA
- $116,000 to $180,000 USD / year
One of Insight Global’s clients is seeking a Senior ASIC Design Engineer to join its R&D engineering team in Vancouver, WA. This individual will be a senior, hands-on contributor…
Added 2 days ago
Senior Specialist, Electrical Engineer- FPGA
L3Harris Technologies
Rochester, NY
L3harris is seeking signal processing focused digital design and verification engineers to support our development of tactical communication products. The candidate will function in an FPGA…
Added 3 days ago
ASIC DFT Engineer
Cisco Systems, Inc.
Austin, TX · San Jose, CA
…central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms - like Silicon…

Apple

SOC Design Verification Engineer

Irvine, CA, United States
San Diego, CA, United States
Sunnyvale, CA, United States
Waltham, MA, United States

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Job details

Experience: BS and a minimum of 10 years relevant industry experience.
Posting language: English
Posted: Oct 27, 2026

Original job description

Summary Apple’s wireless chip powers connectivity across every new iPhone - and its successor is already taking shape. Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization owns every aspect of wireless silicon development, with a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level. It is driven by a world-class, vertically integrated team spanning RF/Analog, Systems/PHY/MAC, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. As a Wireless SOC Design Verification Engineer, you’ll be at the heart of the chip design effort - owning a meaningful verification scope and growing it project to project.

Description You’ll be responsible for pre-silicon RTL verification at the block, subsystem, and top-level SOC, taking your scope from test planning through coverage closure and signoff. Working closely with architects, designers, and firmware engineers, you’ll build reusable testbenches and verification environments using modern, metric-driven methodology. Areas you may work on include the Power Management Unit, CPU subsystem, DMA, on-chip debug infrastructure, PCIe, bus fabric, boot and secure-boot sequencing, MAC-PHY Verification, Radio integration, and peripherals such as SPI - choosing simulation, formal, or whichever approach the design actually calls for. Low power is part of your scope wherever it shows up: you’ll verify power intent using UPF within your area.

Over time, you can grow deeper into the IPs and subsystems you know best, or broader - across IPs and up from block level to full SOC integration. The team is also pushing hard on AI-assisted verification, and you’ll help figure out where it fits best: test generation, debug, coverage closure, or all the above.

Responsibilities

Partner with architects and designers early to build detailed verification plans from specifications - before RTL lands, not after. Develop reusable block/IP and subsystem-level UVM testbenches, and support IP integration into the SOC. Write directed and constrained-random tests; create and analyze coverage models and drive coverage closure. Debug failures, including corner cases, and manage bug tracking through resolution. Verify low-power design intent using UPF within your scope. Verify end-to-end WiFi and Bluetooth traffic flows from subsystem level up through top-level SOC integration. Apply formal verification where it fits - the team will help you ramp up. Build and improve automated regression flows and contribute to methodology in your area. Explore and apply AI-assisted verification techniques to improve team productivity. Participate in verification reviews and uphold high coding-quality standards. Support post-silicon bring-up as needed.

Minimum Qualifications BS and a minimum of 10 years relevant industry experience. Hands-on experience across the verification cycle: test planning, testbench implementation, test creation and debug, and coverage closure. Strong SystemVerilog and Verilog skills, with solid working knowledge of UVM. Solid problem-solving and debugging skills with constrained-random verification. Understanding of digital logic design, SOC architecture, and microarchitecture.

Preferred Qualifications Experience taking at least one ASIC/SOC from concept through tape-out. Verification experience with PCIe, bus fabric/NOC, or AHB/AXI-based architectures in a UVM environment. Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC, or knowledge of wireless protocols. Experience with low-power verification, UPF, boot-up, power-cycling, and HW/FW interaction. Experience with SystemVerilog Assertions (SVA) and/or formal tools (e.g., JasperGold). Experience defining coverage space and writing coverage models. Experience with embedded CPU verification; programming in C/C++ or assembly. Scripting in Python or Perl; interest in applying AI/ML to verification workflows Great teammate with excellent communication skills and the desire to take on diverse challenges.

Pay & Benefits At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,000 and $308,500, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

EEO Statement Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

Accessibility At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here - in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about accessibility in Apple’s workplace

Learn about reasonable accommodations for job applicants

Application Deadline Apple accepts applications to this posting on an ongoing basis.

Pay & Benefits At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $184,700 and $324,800, and your base pay will depend on your skills, qualifications, experience, and location.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Pay & Benefits At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $165,800 and $292,400, and your base pay will depend on your skills, qualifications, experience, and location.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

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More about this job

Skills

RTL
Firmware
SystemVerilog
Verilog
Problem solving
Debugging
C
C++
Assembly
Python
Perl
ML
Communication skills

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